Background Calibration of Comparator Offsets in SHA-Less Pipelined ADCs

Zhu, Congyi; Lin, Jun; Wang, Zhongfeng

doi:10.1109/tcsii.2018.2854571

Cited by 7 publications

(2 citation statements)

References 15 publications

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“…Digital communication systems and instrumentation applications promote the development of highperformance analog-to-digital converters (ADCs) [1,2,3]. Among many ADC architectures, Pipelined ADC is very suitable for high-speed and high-precision operations.…”

Section: Introductionmentioning

confidence: 99%

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An interstage gain calibration technique for pipelined ADCs exploiting complementary dithering and calibration windows detector

Zhai,

Jia,

Guo

et al. 2024

IEICE Electron. Express

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In this paper, a complementary dithering technique is proposed which utilizes LMS digital background calibration method to correct the interstage gain errors in pipeline analog-to-digital converters (ADCs). It not only has a better scattering effect on spectral spurs but also eliminates the increment of residual amplitude caused by dither injection, which will greatly alleviate the design requirements of residual amplifier. Simultaneously, the comparator resolving time nature is utilized to construct calibration windows, which averts the use of duplicate comparators and its digital logic is simple. Behavioral simulation results of 12-bit, 1.25 GS/s pipelined ADC manifest that the proposed calibration technique enhances SNDR and SFDR from 44.27dB and 49.43dB to 70.8dB and 115.3dB respectively.

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Section: Introductionmentioning

confidence: 99%

“…Meanwhile, as the CMOS technology keeps scaling down, high-gain amplifiers become increasingly toilsome to design. The two seriously deteriorate the linearity of pipelined ADC [1,4]. In order to boost the performance of high-speed pipelined ADCs, calibration techniques are needed.…”

Section: Introductionmentioning

confidence: 99%