Berti: an Accurate Local-Delta Data Prefetcher

Navarro-Torres, Agustín; Panda, Biswabandan; Alastruey-Benedé, Jesús; Ibáñez, Pablo; Viñals-Yúfera, Víctor; Ros, Alberto

doi:10.1109/micro56248.2022.00072

Cited by 25 publications

(4 citation statements)

References 40 publications

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“…But ECHO also made important progress for general data prefetching mechanisms. Berti (Navarro-Torres et al, 2022) is a novel first-level data cache prefetcher that brings many advantages with respect to state-of-the-art prefetching mechanisms.…”

Section: Fast and Efficient Memory Operations With Prefetch And Fusionmentioning

confidence: 99%

Towards faster, greener and easier to program computers

Ros

2023

The Project Repository Journal

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Towards faster, greener and easier to program computers The ERC Consolidator Grant project ECHO (Extending Coherence for Hardware-Driven Optimizations in Multicore Architectures) aims to change the events that occur in multiprocessors such that predictions or decisions being made by the processing units will find the best possible outcome in the future. This way, large performance and energy improvements are expected in future computers leveraging ECHO concepts.

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Section: Fast and Efficient Memory Operations With Prefetch And Fusionmentioning

confidence: 99%

Towards faster, greener and easier to program computers

Ros

2023

The Project Repository Journal

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“…Prefetchers can be classified into different types based on their prefetching strategies, where the most common used types are temporal prefetchers and spatial prefetchers [23], [24], [25], [26], [27].…”

Section: Hardware Prefetchersmentioning

confidence: 99%

RL-CoPref: A Reinforcement Learning-based Coordinated Prefetching Controller for Multiple Prefetchers

Fang

Cai

et al. 2023

Preprint

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Modern processors employ data prefetchers to alleviate the impact of long memory access latency. However, current prefetchers are designed for specific memory access patterns, which perform poorly on mixed applications with multiple memory access patterns. To address these issues, RL-CoPref, a reinforcement learning (RL)-based coordinated prefetching controller for multiple prefetchers, is proposed in this paper. RL-CoPref takes diverse program context information as the input, learns to maximize cumulative rewards, and evaluates prefetch quality based on prefetch hits/misses and memory bandwidth utilization. It can dynamically adjust the prefetch activation and prefetch degree, enabling multiple prefetchers to complement each other on mixed applications. Our extensive evaluation, utilizing the ChampSim simulator, demonstrates that RL-CoPref can effectively adapt to various workloads and system configurations, optimizing prefetch control. On average, RL-CoPref achieves 76.15% prefetch coverage, having 35.50% IPC improvement, outperforming state-of-the-art individual prefetchers by 5.91%−16.54% and outperforming SBP, a state-of-the-art (non-RL) prefetch controller, by 4.64%.

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“…The convergence to ChampSim is especially interesting to the community as it provides a reasonably complex simulator that models a non-trivial pipeline and features state-of-the-art cache replacement policies and data/instruction prefetchers, and is therefore quite convenient for the first order study of those "bolt-on" microarchitectural structures. Case in point, several papers published in top-tier conferences have used ChampSim as their experimental workbench [20][21][22][23][24][25][26][27][28][29].…”

Section: *Institute Of Engineering Univ Grenoble Alpesmentioning

confidence: 99%

Rebasing Microarchitectural Research with Industry Traces

Feliu,

Perais,

Jiménez

et al. 2023

2023 IEEE International Symposium on Workload Characterization (IISWC)

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Microarchitecture research relies on performance models with various degrees of accuracy and speed. In the past few years, one such model, ChampSim, has started to gain significant traction by coupling ease of use with a reasonable level of detail and simulation speed. At the same time, datacenter class workloads, which are not trivial to set up and benchmark, have become easier to study via the release of hundreds of industry traces following the first Championship Value Prediction (CVP-1) in 2018. A tool was quickly created to port the CVP-1 traces to the ChampSim format, which, as a result, have been used in many recent works. In this paper, we revisit this conversion tool and find that several key aspects of the CVP-1 traces are not preserved by the conversion. We therefore propose an improved converter that addresses most conversion issues as well as patches known limitations of the CVP-1 traces themselves. We evaluate the impact of our changes on two commits of ChampSim, with one used for the first Instruction Championship Prefetching (IPC-1) in 2020. We find that the performance variation stemming from higher accuracy conversion is significant.

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Berti: an Accurate Local-Delta Data Prefetcher

Cited by 25 publications

References 40 publications

Towards faster, greener and easier to program computers

Towards faster, greener and easier to program computers

RL-CoPref: A Reinforcement Learning-based Coordinated Prefetching Controller for Multiple Prefetchers

Rebasing Microarchitectural Research with Industry Traces

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