Better than one operation per clock (panel)

Abstract

In the 198Os, considerable advances were made in both software and hardware technology, and CPUs that can issue no more than one operation per clock cycle are rapidly approaching this barrier. Further improvements to uniprocessor performance can be obtained by enhancing the architecture of the CPU to allow multiple operations to be issued in a single clock cycle. The focus of this panel is to discuss three architectural approaches to issuing multiple operations per cycle: 6) vector instructions, (ii) very long instruction words (VLIW), and (iii) superscalar execution. We have asked the panelists to address several issues from the vantage point of their preferred architectural approach. These include: