BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture

Abstract

We present Bilkent reconfigurable computer (BilRC), a new coarse-grained reconfigurable architecture (CGRA) employing an execution-triggering mechanism. A control data flow graph language is presented for mapping the applications to BilRC. The flexibility of the architecture and the computation model are validated by mapping several real-world applications. The same language is also used to map applications to a 90-nm field-programmable gate array (FPGA), giving exactly the same cycle count performance. It is found that BilRC reduces the configuration size about 33 times. It is synthesized with 90-nm technology, and typical applications mapped on BilRC run about 2.5 times faster than those on FPGA. It is found that the cycle counts of the applications for a commercial very long instruction word digital signal processor processor are 1.9 to 15 times higher than that of BilRC. It is also found that BilRC can run the inverse discrete cosine transform algorithm almost 3 times faster than the closest CGRA in terms of cycle count. Although the area required for BilRC processing elements is larger than that of existing CGRAs, this is mainly due to the segmented interconnect architecture of BilRC, which is crucial for supporting a broad range of applications. Index Terms-Coarse-grained reconfigurable architectures (CGRA), discrete cosine transform (DCT), fast Fourier transform (FFT), reconfigurable computing, turbo decoder, Viterbi decoder. I. INTRODUCTION T O COMPLY with the performance requirements of emerging applications and evolving communication standards, various architecture alternatives are available. Field-programmable gate arrays (FPGAs) lack run-time programmability, but they compete with their large number of logic resources. To maximize the device utilization, FPGA designers partition the available resources among several sub-applications in such a manner that each application works at the chosen clock frequency and complies with the throughput requirement. The design phases of FPGAs and application-specific integrated circuits (ASICs) are quite similar except that ASICs lack post-silicon flexibility. Unable to exploit the space dimension, digital signal processors (DSPs) fail to provide the performance requirement of many applications due to the limited parallelism that a sequential architecture can provide. This limitation is not due to the Manuscript

A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective

“…BilRC [93] is a heterogeneous mesh composed of three different blocks: generic ALU blocks, Multiplication/Shifter nodes, and memory blocks, following the (by now) traditional recipe of a CGRA. Unique to BilRC is that the architecture explicitly exposes the triggering of instructions, allowing the programmer and/or application fine-grained control over the amount of parallelism or when instructions are executed.…”

The Principle and Progress of Dynamically Reconfigurable Computing Technologies

“…To improve the implementation performance, researchers proposed CGRAs that have coarse-grained reconfigurable cells. There have been many CGRA instances, such as FLEXDET [29] , Morphosys [30] , ADRES [31] , KressArray [32] , BilRC [33] , PACT XPP [34] , DySER [35] , etc. These CGRAs are mostly designed for specific application domains and have special operator structures and interconnection according to the application requirements.…”

Stream Processing Dual-Track CGRA for Object Inference

“…BilRC [17] and Elastic CGRA [18] can be categorized into another CGRA template. Both of them are similar to commercial FPGA in architecture arrangement and configuration manner.…”

“…An approach such as placing multipliers and ALUs in different part, e.g. BilRC [17], would increase the routing resource requirements and even lead to the placement or routing conflict. As a result, the tightly couple of multiplier and ALU for our applications is a proper approach.…”