Binary acceleration using coarse-grained reconfigurable architecture

Paek, Jong Kyung; Choi, Ki‐Young; Lee, Jong-Eun

doi:10.1145/1926367.1926374

Cited by 12 publications

(8 citation statements)

References 21 publications

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“…Paek et al [24] implement a coarse-grained array of homogeneous FUs with a static interconnection scheme. Reconfiguration occurs at runtime according to information extracted from binaries disassembled offline.…”

Section: Related Workmentioning

confidence: 99%

Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems

Bispo

Paulino

Cardoso

et al. 2013

IEEE Trans. Ind. Inf.

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This paper presents a novel approach to accelerate program execution by mapping repetitive traces of executed instructions, called Megablocks, to a runtime reconfigurable array of functional units. An offline tool suite extracts Megablocks from microprocessor instruction traces and generates a Reconfigurable Processing Unit (RPU) tailored for the execution of those Megablocks. The system is able to transparently movebcomputations from the microprocessor to the RPU at runtime. A prototype implementation of the system using a cacheless MicroBlaze microprocessor running code located in external memory reaches speedups from to for a set of 14 benchmark kernels. For a system setup which maximizes microprocessor performance by having the application code located in internal block RAMs, speedups from to were estimated.

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Section: Related Workmentioning

confidence: 99%

Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems

Bispo

Paulino

Cardoso

et al. 2013

IEEE Trans. Ind. Inf.

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“…More recently, some works proposed the use of binary translation to provide software compatibilty for CGRAs [5,30]. Binary translation converts code compiled from a source ISA to run in a different ISA.…”

Section: Introductionmentioning

confidence: 99%

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

Ferreira

Denver

Pereira

et al. 2015

J Sign Process Syst

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In the past years, many works have demonstrated the applicability of Coarse-Grained Reconfigurable Array (CGRA) accelerators to optimize loops by using software pipelining approaches. They are proven to be effective in reducing the total execution time of multimedia and signal processing applications. However, the run-time reconfigurability of CGRAs is hampered overheads introduced by the needed translation and mapping steps. In this work, we present a novel run-time translation technique for the modulo scheduling approach that can convert binary code onthe-fly to run on a CGRA. We propose a greedy approach, since the modulo scheduling for CGRA is an NP-complete problem. In addition to read-after-write dependencies, the dynamic modulo scheduling faces new challenges, such as register insertion to solve recurrence dependences and to balance the pipelining paths. Our results demonstrate that the greedy run-time algorithm can reach a near-optimal ILP rate, better than an off-line compiler approach for a 16-issue VLIW processor. The proposed mechanism ensures software compatibility as it supports different source ISAs. As proof of concept of scaling, a change in the memory bandwidth has been evaluated. In this analysis it is demonstrated R. Ferreira ( ) · W. Denver that when changing from one memory access per cycle to two memory accesses per cycle, the modulo scheduling algorithm is able to exploit this increase in memory bandwidth and enhance performance accordingly. Additionally, to measure area and performance, the proposed CGRA was prototyped on an FPGA. The area comparisons show that a crossbar CGRA (with 16 processing elements and including an 4-issue VLIW host processor) is only 1.11 × bigger than a standalone 8-issue VLIW softcore processor.

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“…Recent works proposed the use of binary translation as a solution to reduce the intrinsic performance overhead of CGRA [12], [13]. Binary translation converts code compiled to a source ISA to run in a different ISA, in order to ensure software compatibility between different versions, or to allow application execution in different ISAs without the need for code recompilation.…”

Section: Introductionmentioning

confidence: 99%

A run-time modulo scheduling by using a binary translation mechanism

Ferreira

Denver

Pereira

et al. 2014

2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)

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It is well known that innermost loop optimizations have a big effect on the total execution time. Although CGRAs is widely used for this type of optimizations, their usage at run-time has been limited due to the overheads introduced by application analysis, code transformation, and reconfiguration. These steps are normally performed during compile time. In this work, we present the first dynamic translation technique for the modulo scheduling approach that can convert binary code on-the-fly to run on a CGRA. The proposed mechanism ensures software compatibility as it supports different source ISAs. As proof of concept of scaling, a change in the memory bandwidth has been evaluated (from one memory access per cycle to two memory accesses per cycle). Moreover, a comparison to the state-of-the-art static compiler-based approaches for inner loop accelerators has been done by using CGRA and VLIW as target architectures. Additionally, to measure area and performance, the proposed CGRA was prototyped on a FPGA. The area comparisons show that crossbar CGRA (with 16 processing elements) is 1.9x larger than the VLIW 4-issue and 1.3x smaller than a VLIW 8-issue softcore processor, respectively. In addition, it reaches an overall speedup factor of 2.17x and 2.0x in comparison to the 4 and 8-issue, respectively. Our results also demonstrate that the runtime algorithm can reach a near-optimal ILP rate, better than an off-line compiler approach for an n-issue VLIW processor.

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Binary acceleration using coarse-grained reconfigurable architecture

Cited by 12 publications

References 21 publications

Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems

Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

A run-time modulo scheduling by using a binary translation mechanism

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