BIST Architecture for Multiple RAMs in SoC

John, Preethy K; Rony, Antony P

doi:10.1016/j.procs.2017.09.121

Cited by 17 publications

(4 citation statements)

References 4 publications

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“…Lygiagretus savitestavimas. Centralizuoto ir atskirtojo savitestavimo sistema (John, Antony, 2017) naudoja vieną signalų generavimo ir duomenų apdorojimo grandyną daugeliui testuojamų sistemų (1.2 pav.). Vienu metu yra testuojama viena sistema, o testuojamos sistemos yra perjungiamos naudojant multipleksorius.…”

Section: Savitestavimo Būdai Ir Sistemosunclassified

Belaidžio ryšio siųstuvų-imtuvų filtrų savitestavimo ir autokalibravimo metodų sukūrimas ir tyrimas

Kladovščikov¹

2020

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Section: Savitestavimo Būdai Ir Sistemosunclassified

Belaidžio ryšio siųstuvų-imtuvų filtrų savitestavimo ir autokalibravimo metodų sukūrimas ir tyrimas

Kladovščikov¹

2020

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“…Preethy K John et al, [11] proposed a fault detection algorithm for memory cores using March -C algorithm. A Configurable Linear Feedback Shift Register (CLFSR) is used to generate the addresses to achieve maximum coverage.…”

Section: March Test Algorithmsmentioning

confidence: 99%

Design and Development of A Modified AXI Based BIST Technique for Memory Architectures

Rayudu*,

‘G,

Rao

2019

IJRTE

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Memory testing and fault detection is an important phase in testing the hardware devices. This improves the overall performance of the system and prevents runtime failures in the devices. Built In Self Test (BIST) is a hardware memory test architecture deployed in many System on Chip devices to enable fault detection. This technique reduces the cost and time needed to test the memory systems. Different BIST modules need to be used to detect faults in different memories. As a result, design complexity increases. In order to overcome these above shortcomings, it is essential to develop advanced extensible Interface (AXI) with Block Random Access Memory (BRAM) and Design and Develop AXI based self-test memory architecture (March Algorithms) to achieve parallel read and write capability. The proposed model reduced the dynamic power and the clock cycles needed for simulation when compared to existing techniques

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“…However, for designing ASIC or any complex chip, Design for Testability (DFT) is a prime concern because testing a VLSI chip using Automatic Test Equipment (ATE) is highly complex, time-consuming as well as expensive [ 23 , 24 ]. To deal with the testing problem at the chip level, incorporating Built-in Self-Test (BIST) capability inside a chip is a widely accepted approach [ 25 – 30 ] and it is a norm of this day in the VLSI industry. BIST is a mode of operation of a chip other than its normal mode, where when a chip is switched to this mode, it performs its test by itself.…”

Section: Introductionmentioning

confidence: 99%

Design of a BIST implemented AES crypto-processor ASIC

2021

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This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.

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BIST Architecture for Multiple RAMs in SoC

Cited by 17 publications

References 4 publications

Belaidžio ryšio siųstuvų-imtuvų filtrų savitestavimo ir autokalibravimo metodų sukūrimas ir tyrimas

Belaidžio ryšio siųstuvų-imtuvų filtrų savitestavimo ir autokalibravimo metodų sukūrimas ir tyrimas

Design and Development of A Modified AXI Based BIST Technique for Memory Architectures

Design of a BIST implemented AES crypto-processor ASIC

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