Bit-Parallel Vector Composability for Neural Acceleration

Ghodrati, Soroush; Sharma, Hardik; Young, Cliff; Kim, Nam Sung; Esmaeilzadeh, Hadi

doi:10.1109/dac18072.2020.9218656

Cited by 19 publications

(5 citation statements)

References 14 publications

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“…Bitfusion [14], DNPU [11]), and it's better to have BG unrolling at L3 for lower frequencies (e.g. BitBlade [15], Ghodrati [17]) or temporally unrolling BGs for higher frequencies (e.g. Loom [16], Stripes [25]).…”

Section: Discussionmentioning

confidence: 99%

“…With such a template, one can stop at L3 for a smaller MAC array size, go for L4 for a standard array, or even extend to higher levels for a larger array. Additionally, having a small L1 unit allows us to have precision-scalable MAC units that can go down to 2-bit precision, which is the lowest precision supported in most precision-scalable accelerators [14], [15], [17], [21]. Furthermore, this multi-level architecture will later give a clear perspective of where each CNN loop gets unrolled to.…”

Section: A Highly Parameterized Psma Templatementioning

confidence: 99%

“…Additionally, at low precisions, BitFusion's L2 is output shared, while DNPU's L2 is input/weight shared. BitBlade [15] and Ghodrati [17] have a very similar PSMA architecture, and thus are mapped the same way in the new taxonomy. In their works, the shifters are shared between L2 units at L3, thus their BG is unrolled spatially at L3.…”

Section: F Complete Taxonomy and Sota Mappingmentioning

confidence: 99%

“…Many precision-scalable accelerators were proposed over the past years, some of which support weight-only (1D) precision scalability [11]- [13], or input/weight (2D) precision scalability [14]- [17]. As all these precision scalable MACs have been demonstrated with different RTL coding styles, in different silicon technologies, in different MAC array configurations, and with different DNN workloads, it is hard to relatively compare them in terms of their drawbacks and merits.…”

Section: Introductionmentioning

confidence: 99%

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Taxonomy and Benchmarking of Precision-Scalable MAC Arrays Under Enhanced DNN Dataflow Representation

Ibrahim,

Mei,

Verhelst

2021

Preprint

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Reduced-precision and variable-precision multiplyaccumulate (MAC) operations provide opportunities to significantly improve energy efficiency and throughput of DNN accelerators with no/limited algorithmic performance loss, paving a way towards deploying AI applications on resource-constraint edge devices. Accordingly, various precision-scalable MAC array (PSMA) architectures were recently proposed. However, it is difficult to make a fair comparison between those alternatives, as each proposed PSMA is demonstrated in different systems with different technologies. This work aims to provide a clear view on the design space of PSMA and offer insights for selecting the optimal architectures based on designers' needs. First, we introduce a precision-enhanced for-loop representation for DNN dataflows. Next, we use this new representation towards a comprehensive PSMA taxonomy, capable to systematically cover most prominent state-of-the-art PSMAs, as well as uncover new PSMA architectures. Following that, we build a highly parameterized PSMA template that can be design-time configured into a huge subset of the design space spanned by the taxonomy. This allows to fairly and thoroughly benchmark 72 different PSMA architectures. We perform such studies in 28nm technology targeting run-time precision scalability from 8 to 2 bits, operating at 200 MHz and 1 GHz. Analyzing resulting energy efficiency and area breakdowns reveals key design guidelines for PSMA architectures.

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Section: Discussionmentioning

confidence: 99%

Section: A Highly Parameterized Psma Templatementioning

confidence: 99%

Section: F Complete Taxonomy and Sota Mappingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Taxonomy and Benchmarking of Precision-Scalable MAC Arrays Under Enhanced DNN Dataflow Representation

Ibrahim,

Mei,

Verhelst

2021

Preprint

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“…Bit-manipulation primitives have been used in enhancing the performance of deep neural networks (DNNs) on GPUs [36]- [38], ASICs, and FPGAs [39]- [41]. They are about dense binary operations, so they cannot efficiently handle sparse ops as those in graph processing.…”

Section: Background and Related Workmentioning

confidence: 99%

Bit-GraphBLAS: Bit-Level Optimizations of Matrix-Centric Graph Processing on GPU

Chen¹,

Sung²,

Shen³

et al. 2022

Preprint

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In a general graph data structure like an adjacency matrix, when edges are homogeneous, the connectivity of two nodes can be sufficiently represented using a single bit. This insight has, however, not yet been adequately exploited by the existing matrix-centric graph processing frameworks. This work fills the void by systematically exploring the bit-level representation of graphs and the corresponding optimizations to the graph operations. It proposes a two-level representation named Bit-Block Compressed Sparse Row (B2SR) and presents a series of optimizations to the graph operations on B2SR by leveraging the intrinsics of modern GPUs. Evaluations on NVIDIA Pascal and Volta GPUs show that the optimizations bring up to 40× and 6555× for essential GraphBLAS kernels SpMV and SpGEMM, respectively, making GraphBLAS-based BFS accelerate up to 433×, SSSP, PR, and CC up to 35×, and TC up to 52×.

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