Blind estimation of unknown time delay in periodic non-uniform sampling: Application to desynchronized time interleaved-ADCs

Vernhes, Jean-Adrien; Chabert, Marie; Lacaze, B.; Lesthievent, Guy; Baudin, Roland; Boucheret, Marie‐Laure

doi:10.1109/icassp.2016.7472524

Cited by 5 publications

(2 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The output of the error detection algorithm is proportional to the sampling time error and then, it does not correspond to the exact value of the error. We propose the error detection and correction in an LMS loop to minimize x 2 1 À x 2 2 . The timing error detection algorithm is applied after the interpolator.…”

Section: Timing Error Correctionmentioning

confidence: 99%

See 1 more Smart Citation

Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC

Abbaszadeh

Aghdam

Muñoz

2019

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

Sample time error can degrade the performance of time-interleaved analog to digital converters (TIADCs). A fully digital background algorithm is presented in this paper to estimate and correct the timing mismatch errors between four interleaved channels, together with its hardware implementation. The proposed algorithm provides low computation burden and high performance. It is based on the simplified representation of the coefficients of the Lagrange interpolator. Simulation results show that it can suppress error tones in all of the Nyquist band. Results show that, for a four-channel TIADC with 10-bit resolution, the proposed algorithm improves the signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) by 19.27 dB and 35.2 dB, respectively. This analysis was done for an input signal frequency of 0:09f s. In the case of an input signal frequency of 0:45f s , an improvement by 33.06 dB and 43.14 dB is respectively achieved in SNDR and SFDR. In addition to the simulation, the algorithm was implemented in hardware for real-time evaluation. The low computational burden of the algorithm allowed an FPGA implementation with a low logic resource usage and a high system clock speed (926.95 MHz for four channel algorithm implementation). Thus, the proposed architecture can be used as a post-processing algorithm in host processors for data acquisition systems to improve the performance of TIADC.

show abstract

Section: Timing Error Correctionmentioning

confidence: 99%

“…This is achieved by moving the analog to digital converter (ADC) closer to the antenna for high-frequency and wide-bandwidth systems [1]. For this reason, the sampling rate and bit resolution of ADCs might become a bottleneck in modern communication systems [2].…”

Section: Introductionmentioning

confidence: 99%