Blue Gene/L torus interconnection network

Abstract

The main interconnect of the massively parallel Blue Genet/L is a three-dimensional torus network with dynamic virtual cut-through routing. This paper describes both the architecture and the microarchitecture of the torus and a network performance simulator. Both simulation results and hardware measurements are presented.

An RMS Architecture for Efficiently Supporting Complex-Moldable Applications

“…First, CooRM assumes that clusters are perfectly homogeneous and that the choice of host IDs inside a cluster can be left to the RMS. However, large clusters and supercomputers feature non-homogeneous networks (such as a 3D torus [4]) with varying latencies and bandwidths between hosts. While research is still in progress, in future, applications might want to optimize their resource selection for an efficient placement inside non-homogeneous clusters.…”

“…The RMS shall eventually allocate resources to the application, guaranteeing exclusive, non-preempted access for the given duration. Requests never fail, their start-time is arbitrarily delayed until their allocation can be fulfilled 4 . The application is allowed to terminate earlier, however, the RMS shall kill an application exceeding its allocation.…”

Impact of Predictive Switching in 2-D Torus Networks

“…In this scenario, shortened cycles may be limited to RC cycles. However, a deserialization latency is not negligible for narrow channel routers because a packet header is composed 1 The multiple cycles for the RC stage include deserialization for the packet header phits.…”

“…For example, BlueGene/L processes packet headers in an eight-stage input pipeline [1]. It needs to update hint bits that are used for lookahead routing at each router before the packet header is sent out.…”

“…In the case of non-predictive switching, each router hops the packet in five pipeline stages: input buffering (IB), routing computation (RC), output virtual channel allocation (VC), switch allocation (SA), and switch traversal (ST). We also assume that the RC stage requires three cycles to process a packet header 1 , and the other stages take one cycle per phit. Therefore, router-A executes VA and SA stages in cycles 4 and 5, respectively, followed by ST stages from cycle 6 to 13.…”