Bounded model checking for fixed-point digital filters

Abreu, Renato; Gadelha, Mikhail R.; Cordeiro, Lucas C.; Filho, Eddie B. de Lima; Silva, Waldir Sabino da

doi:10.1186/s13173-016-0041-8

Cited by 19 publications

(27 citation statements)

References 31 publications

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“…In order to tackle such problem, this paper proposes a verification methodology based on bounded model checking (BMC) techniques [11], which verifies properties on statespace digital controllers, by means of a verification tool named as Digital-Systems Verifier (DSVerifier). It is worth noting that this paper extends a previous work [7,18,2,13,6]. In particular, the major improvement of the DSVerifier version described here relies on the support for state-space models, which allows a better insight about the internal system behavior, enables the verification of new properties (e.g., controllability and observability), and considers initial conditions for system analysis [14].…”

Section: Motivationmentioning

confidence: 64%

“…In contrast, Alur et al [3,4] proposed the prior automated verification approaches, regarding model checking, which inspired the development of other verifiers for cyber-physical systems and hybrid automata (e.g., Maellan [32], Open-Kronos [33], and UPPAAL [5]). Nonetheless, differently from the work presented here, such approaches do not tackle system robustness related to implementation aspects [7,18,2].…”

Section: Background and Related Workmentioning

confidence: 95%

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Bounded model checking of state-space digital systems: the impact of finite word-length effects on the implementation of fixed-point digital controllers based on state-space modeling

Monteiro

2016

Proceedings of the 2016 24th ACM SIGSOFT International Symposium on Foundations of Software Engineering

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The extensive use of digital controllers demands a growing effort to prevent design errors that appear due to finiteword length (FWL) effects. However, there is still a gap, regarding verification tools and methodologies to check implementation aspects of control systems. Thus, the present paper describes an approach, which employs bounded model checking (BMC) techniques, to verify fixed-point digital controllers represented by state-space equations. The experimental results demonstrate the sensitivity of such systems to FWL effects and the effectiveness of the proposed approach to detect them. To the best of my knowledge, this is the first contribution tackling formal verification through BMC of fixed-point state-space digital controllers.

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Section: Motivationmentioning

confidence: 64%

Section: Background and Related Workmentioning

confidence: 95%

Bounded model checking of state-space digital systems: the impact of finite word-length effects on the implementation of fixed-point digital controllers based on state-space modeling

Monteiro

2016

Proceedings of the 2016 24th ACM SIGSOFT International Symposium on Foundations of Software Engineering

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“…Depending on the selected solver, the results, verification time, and counterexamples can be different. This is observed in several studies [28,59,60,67]; as a result, our evaluation here is also carried out using different SMT solvers such as Boolector [15], Z3 [14], and Math-SAT [16], in order to check whether a particular solver heavily influences the performance of the CEGIO algorithms.…”

Section: Experimental Evaluationmentioning

confidence: 96%

“…In addition to software verification, ESBMC has been applied to ensure correctness of digital filters and controllers [59][60][61]. Recently, ESBMC has been applied to optimize HW/SW co-design [26][27][28].…”

Section: Definition 5 a Counterexample For A Property φ Is A Sequence Smentioning

confidence: 99%

Counterexample guided inductive optimization based on satisfiability modulo theories

Araujo

Albuquerque

Bessa

et al. 2018

Science of Computer Programming

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This paper describes three variants of a counterexample guided inductive optimization (CEGIO) approach based on Satisfiability Modulo Theories (SMT) solvers. In particular, CEGIO relies on iterative executions to constrain a verification procedure, in order to perform inductive generalization, based on counterexamples extracted from SMT solvers. CEGIO is able to successfully optimize a wide range of functions, including non-linear and non-convex optimization problems based on SMT solvers, in which data provided by counterexamples are employed to guide the verification engine, thus reducing the optimization domain. The present algorithms are evaluated using a large set of benchmarks typically employed for evaluating optimization techniques. Experimental results show the efficiency and effectiveness of the proposed algorithms, which find the optimal solution in all evaluated benchmarks, while traditional techniques are usually trapped by local minima.

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“…Such behavior is due to quantization errors caused by a more constrained precision, which result in coefficients that are different from the ones originally designed. As result, one may argue about the effectiveness of digital filters and the number of bits needed for their representation, in such a way that design parameters are satisfied [16]. This paper presents a verification methodology for digital filters with fixed-point implementation, based on the Efficient SMT-Based Context-Bounded Model Checker (ESBMC), which employs Bounded Model Checking (BMC) techniques and Satisfiability Modulo Theories (SMT) [3], [4].…”

Section: Introductionmentioning

confidence: 99%

Verification of Magnitude and Phase Responses in Fixed-Point Digital Filters

Mello¹,

Freitas²,

Cordeiro³

et al. 2017

Anais De XXXV Simpósio Brasileiro De Telecomunicações E Processamento De Sinais

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In the digital signal processing (DSP) area, one of the most important tasks is digital filter design. Currently, this procedure is performed with the aid of computational tools, which generally assume filter coefficients represented with floating-point arithmetic. Nonetheless, during the implementation phase, which is often done in digital signal processors or field programmable gate arrays, the representation of the obtained coefficients can be carried out through integer or fixed-point arithmetic, which often results in unexpected behavior or even unstable filters. The present work addresses this issue and proposes a verification methodology based on the digital-system verifier (DSVerifier), with the goal of checking fixed-point digital filters w.r.t. implementation aspects. In particular, DSVerifier checks whether the number of bits used in coefficient representation will result in a filter with the same features specified during the design phase. Experimental results show that errors regarding frequency response and overflow are likely to be identified with the proposed methodology, which thus improves overall system's reliability.

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Bounded model checking for fixed-point digital filters

Cited by 19 publications

References 31 publications

Bounded model checking of state-space digital systems: the impact of finite word-length effects on the implementation of fixed-point digital controllers based on state-space modeling

Bounded model checking of state-space digital systems: the impact of finite word-length effects on the implementation of fixed-point digital controllers based on state-space modeling

Counterexample guided inductive optimization based on satisfiability modulo theories

Verification of Magnitude and Phase Responses in Fixed-Point Digital Filters

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