Breaking the Bandwidth Limit: A Review of Broadband Doherty Power Amplifier Design for 5G

Nikandish, Gholamreza; Staszewski, Robert Bogdan; Zhu, Anding

doi:10.1109/mmm.2019.2963607

Cited by 78 publications

(41 citation statements)

References 71 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A great deal of efforts has been made by researchers to get an accurate model of lumped inductors and metal-insulator-metal (MIM) capacitors for the Mm-Wave PAs in CMOS technology is well suited for fully integrated 5G phased array transceivers due to low cost and high integrity. To date, significant progress in this field has been made [5][6][7][8][9]. However, the high substrate-induced loss is still a critical challenge for mm-Wave circuits in bulk Si CMOS, which limits the gain and the power efficiency of the PA [6].…”

Section: Cpw Matching Network With Dc-blocking Capacitorsmentioning

confidence: 99%

A 28 GHz Linear Power Amplifier Based on CPW Matching Networks with Series-Connected DC-Blocking Capacitors

Xia

Huang

et al. 2020

Electronics

View full text Add to dashboard Cite

In this paper, the influence of the DC-blocking capacitors leveraged in coplanar waveguide (CPW) matching networks is studied. CPW matching networks with series-connected DC-blocking capacitors are less sensitive to capacitance and are adopted in a 28 GHz power amplifier (PA). The PA targeting fifth-generation (5G) phased array is developed in 90 nm silicon-on-insulator complementary-metal-oxide-semiconductor (SOI CMOS) technology. A stacked field-effect-transistor (FET) architecture is elected in the output stage to boost the output power and reduce the die area. The PA with a core area of 0.31 mm2 demonstrates a maximum small signal gain of 13.7 dB and a −3 dB bandwidth of 6.3 GHz (22.9–29.2 GHz). The PA achieves a measured saturated output power (Psat) of 14.4 dBm and a peak power added efficiency (PAE) of 25% for continuous wave signals. At 24/25.6/28 GHz, the PA achieves +7.87/+9.16/+10.7 dBm measured output power and 6.21%/8.11%/10.17% PAE at −25 dBc error vector magnitude(EVM) for a 250 MHz-wide 64-quadrature amplitude modulation (64-QAM). The developed linear PA provides a great potential for low-cost 5G phased array transceivers.

show abstract

Section: Cpw Matching Network With Dc-blocking Capacitorsmentioning

confidence: 99%

A 28 GHz Linear Power Amplifier Based on CPW Matching Networks with Series-Connected DC-Blocking Capacitors

Xia

Huang

et al. 2020

Electronics

View full text Add to dashboard Cite

show abstract

“…The gate biases of the carrier and peaking transistors are respectively chosen as −2.0 V and −4.0 V. An EVM of −30.5 dB (3%) is achieved at 29.3 dBm average output power and 25.7% average PAE. 3…”

Section: B Modulated-signal Measurementsmentioning

confidence: 99%

“…The associate editor coordinating the review of this article and approving it for publication was Yuhao Liu. employed to accommodate the 5G network speeds approaching tens of gigabits per second (Gb/s). The Doherty power amplifier (DPA) is an effective architecture to achieve high average efficiency in dealing with such signals [2], [3]. The conventional DPAs suffer limited bandwidth mainly arising from the load modulation network.…”

Section: Introductionmentioning

confidence: 99%

“…The conventional DPAs suffer limited bandwidth mainly arising from the load modulation network. Most notable bandwidth enhancement techniques developed for DPAs include modified characteristic impedance of transmission lines in the load modulation network, modified network for the peaking transistor, parasitic capacitance compensation, frequency response optimization, and dual-input DPA architecture [3]. However, most of these solutions are only applicable to discrete circuits.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Bandwidth Enhancement of GaN MMIC Doherty Power Amplifiers Using Broadband Transformer-Based Load Modulation Network

2019

Self Cite

View full text Add to dashboard Cite

In this paper, we present a bandwidth enhancement technique for monolithic microwave integrated circuit (MMIC) Doherty power amplifiers (DPAs) in wireless transmitters. A broadband load modulation network is proposed by exploiting transformers and output-referred parasitic capacitances of the carrier and peaking transistors of DPA. The proposed network comprises two transformers that are used to improve frequency response of the load impedance presented to the carrier transistor at back-off and extend the DPA bandwidth. The network benefits from a unity transformation ratio and it can be readily realized by using edge-coupled microstrip transmission lines. Optimal coupling coefficients of the two transformers are determined based on bandwidth and insertion loss considerations. A proof-of-concept DPA is implemented in a 0.25-µm GaN MMIC process. It achieves 35-36 dBm output power, 42.8-48.7% drain efficiency at peak power and 24.4-31.6% at 6-dB back-off, over 4.5-6.0 GHz bandwidth. When excited by a 100-MHz 64-QAM signal with 8 dB peak-to-average power ratio (PAPR), the DPA exhibits 29.3 dBm average output power and 28.4% average drain efficiency, while the error vector magnitude (EVM) is −30.5 dB (3%) without any predistortion.

show abstract

“…The first two PA architectures realize the load modulation principle in order to improve transmitter efficiency. Due to the possibility of achieving wide operational bandwidth, the Doherty PAs have gained in popularity over the last decades [5]- [7]. Besides, Doherty PAs have a simple single input single output interface, which makes them an attractive approach to replace single-ended PAs, such as class-AB.…”

Section: Introductionmentioning

confidence: 99%

Analysis and Design of Outphasing Transmitter Using Class-E Power Amplifiers With Shunt Capacitances and Shunt Filters

et al. 2020

View full text Add to dashboard Cite

In this paper, a novel outphasing power amplifier (PA) based on class-E amplifiers with shunt capacitances and shunt filters is proposed. The new design provides high drain efficiency for both peak and back-off power levels. A mathematical model for the class-E power amplifier with shunt capacitance and shunt filter is presented. The proposed model enables derivation of load circuit parameters that provide optimum drain efficiency for the peak and back-off power levels using closed form mathematical expressions. Based on this model, an outphasing power amplifier is designed and subsequently implemented using microstrip transmission lines and a GaN HEMT devices. The fabricated power amplifier prototype is optimized for 2.14 GHz and provides drain efficiency of over 60% for back-off power levels up to 8.5 dB. The amplifier demonstrates a 44.3% drain efficiency for 64QAM OFDM modulated signal with 20 MHz bandwidth. Adjacent channel leakage ratio (ACLR) of-39.5 dB and error vector magnitude (EVM) of 0.9 % were achieved after the application of a memory polynomial linearization algorithm.

show abstract

Breaking the Bandwidth Limit: A Review of Broadband Doherty Power Amplifier Design for 5G

Cited by 78 publications

References 71 publications

A 28 GHz Linear Power Amplifier Based on CPW Matching Networks with Series-Connected DC-Blocking Capacitors

A 28 GHz Linear Power Amplifier Based on CPW Matching Networks with Series-Connected DC-Blocking Capacitors

Bandwidth Enhancement of GaN MMIC Doherty Power Amplifiers Using Broadband Transformer-Based Load Modulation Network

Analysis and Design of Outphasing Transmitter Using Class-E Power Amplifiers With Shunt Capacitances and Shunt Filters

Contact Info

Product

Resources

About