BSIM4 parameter extraction for tri-gate Si nanowire transistors

Abstract

We investigated the BSIM4 parameter extraction procedure for tri-gate Si nanowire transistors with different geometries and fabrication processes using measurement data. Dependence of source/drain parasitic resistances on transistor geometry and fabrication process can be observed on the extracted parameters. Single sets of parameters can reproduce I-V characteristics with L g down to 35nm.