BulkSMT: Designing SMT processors for atomic-block execution

Qian, Xuehai; Sahelices, Benjamin; Torrellas, Josep

doi:10.1109/hpca.2012.6168952

Cited by 14 publications

(11 citation statements)

References 27 publications

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“…Intra-Warp Conflict Resolution. Qian et al [29] described a method to detect and resolve conflicts among threads running on SMT CPU cores, which usually have far fewer threads per core in comparison to GPU cores. The relatively small number of threads allows their design to dedicate explicit storage to record the dependency between transactions and extend each cache line to record read-sharer information.…”

Section: Sensitivity To Core Scalingmentioning

confidence: 99%

Energy efficient GPU transactional memory via space-time optimizations

Fung

Aamodt

2013

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

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Many applications with regular parallelism have been shown to benefit from using Graphics Processing Units (GPUs). However, employing GPUs for applications with irregular parallelism tends to be a risky process, involving significant effort from the programmer. One major, non-trivial effort/risk is to expose the available parallelism in the application as 1000s of concurrent threads without introducing data races or deadlocks via fine-grained data synchronization. To reduce this effort, prior work has proposed supporting transactional memory on GPU architectures. One hardware proposal, Kilo TM, can scale to 1000s of concurrent transaction. However, performance and energy overhead of Kilo TM may deter GPU vendors from incorporating it into future designs.In this paper, we analyze the performance and energy efficiency of Kilo TM and propose two enhancements: (1) Warp-level transaction management allows transactions within a warp to be managed as a group. This aggregates protocol messages to reduce communication overhead and captures spatial locality from multiple transactions to increase memory subsystem utility. (2) Temporal conflict detection uses globally synchronized timers to detect conflicts in read-only transactions with low overhead. Our evaluation shows that combining the two enhancements in combination can improve the overall performance and energy efficiency of Kilo TM by 65% and 34% respectively. Kilo TM with the above two enhancements achieves 66% of the performance of fine-grained locking with 34% energy overhead.

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Section: Sensitivity To Core Scalingmentioning

confidence: 99%

Energy efficient GPU transactional memory via space-time optimizations

Fung

Aamodt

2013

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

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“…Currently, there are several proposals that support conflict serialization of atomic blocks, most notably DATM [20], SONTM [4], BulkSMT [18], and Waitn-GoTM [16]. However, they all fall short of the goal of this paper.…”

Section: Introductionmentioning

confidence: 92%

“…There are a few proposals that support conflict serialization of atomic blocks, such as DATM [20], SONTM [4], BulkSMT [18], and Wait-n-GoTM [16]. While each of these schemes advances the state-of-the-art in some directions, none provides an effective approach usable in a distributed directorybased protocol for both software-demarcated atomic blocks (e.g., in TM) and hardware-initiated blocks (e.g., in speculation for strict memory consistency).…”

Section: Existing Proposalsmentioning

confidence: 99%

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OmniOrder: Directory-based conflict serialization of transactions

Qian¹,

Sahelices²,

Torrellas³

2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

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Effective execution of atomic blocks of instructions (also called transactions) can enhance the performance and programmability of multiprocessors. Atomic blocks can be demarcated in software as in Transactional Memory (TM) or dynamically generated by the hardware as in aggressive implementations of strict memory consistency. In most current designs, when two atomic blocks conflict, one is squashed -a performance loss that is often unnecessary.To avoid this waste, this paper presents OmniOrder, the first design that efficiently executes conflicting atomic blocks concurrently in a directory-based coherence environment. The idea is to keep only non-speculative data in the caches and, when the cache coherence protocol transfers a line, include in the message the history of speculative updates to the line. The coherence protocol transitions are unmodified. We evaluate OmniOrder with 64-core simulations. In a TM environment, OmniOrder reduces the execution time of the STAMP applications by an average of 18.4% over a scheme that squashes on conflict. In an environment with SC enforcement with speculation, we run 11 programs that implement concurrent algorithms. OmniOrder reduces the programs' execution time by an average of 15.3% relative to a scheme that squashes on conflict. Finally, OmniOrder's communication overhead of transferring the history of speculative updates is negligible.

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“…The SVC design requires conditional gang invalidation, an uncommon architectural feature which requires circuit-level changes (additional transistors) to the SRAM cell. In a similar vein, BulkSMT [Qian et al 2012] describes a design for supporting simultaneous speculative contexts on a multithreaded core using cache line annotations requiring conditional gang clearing logic based on comparison between multi-bit fields. The Memory Disambiguation Table (MDT) design [Krishnan and Torrellas 1999] requires caches that support both a speculative write-back mode and a nonspeculative write-through mode.…”

Section: Related Workmentioning

confidence: 99%

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Negi

Titos-Gil

2013

ACM Trans. Archit. Code Optim.

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This article describes cache designs for efficiently supporting speculative techniques like transactional memory on chip multiprocessors with multithreaded cores. On-demand allocation and prompt freeing of speculative cache space in the design reduces the burden on nonspeculative execution. Quick access to both clean and speculative versions of data for multiple contexts provides flexibility and greater design freedom to HTM architects. Performance analysis shows the designs stand up well against other HTM design proposals, with potential performance gains in high contention applications with small transactions.

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BulkSMT: Designing SMT processors for atomic-block execution

Cited by 14 publications

References 27 publications

Energy efficient GPU transactional memory via space-time optimizations

Energy efficient GPU transactional memory via space-time optimizations

OmniOrder: Directory-based conflict serialization of transactions

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