Cachet: A High-Performance Joint-Subtree Integrity Verification for Secure Non-Volatile Memory

Kubo, Tatsuya; Takamaeda-Yamazaki, Shinya

doi:10.1109/coolchips57690.2023.10122117

2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) 2023

DOI: 10.1109/coolchips57690.2023.10122117

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Cachet: A High-Performance Joint-Subtree Integrity Verification for Secure Non-Volatile Memory

Tatsuya Kubo

Shinya Takamaeda-Yamazaki

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Cachet: A High-Performance Joint-Subtree Integrity Verification for Secure Non-Volatile Memory

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