2010 19th IEEE Asian Test Symposium 2010
DOI: 10.1109/ats.2010.70
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Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power

Zhiqiang You
1
,
Jiedi Huang
2
,
Michiko Inoue
3
et al.
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Cited by 4 publications
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Hybrid history-based test overlapping to reduce test application time

Janfaza
1
,
Forouzandeh
2
,
Behnam
3
et al. 2013
East-West Design &Amp; Test Symposium (EWDTS 2013)
3
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1
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Hybrid history-based test overlapping to reduce test application time

Janfaza
1
,
Forouzandeh
2
,
Behnam
3
et al. 2013
East-West Design &Amp; Test Symposium (EWDTS 2013)
3
0
1
0
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Hybrid history-based test, utilizing a probabilistic approach to reduce test time

Janfaza
1
,
Sabaghian-Bidgoli
2
,
Baharlouei
3
2017
2017 IEEE East-West Design &Amp; Test Symposium (EWDTS)
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Test Architecture for Fine Grained Capture Power Reduction

Yi
1
,
Jiang
2
,
Ramakrishnan
3
et al. 2019
2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
4
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