Carry-select adder using single ripple-carry adder

Chang, Tsin‐Yuan; Hsiao, Meng-Jie

doi:10.1049/el:19981706

Cited by 150 publications

(73 citation statements)

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“…By keeping this as main point in [5,6,7] RCA"s in second stage of CSLA replaced by binary excess converter (BEC) to achieve lower area and less power dissipation by reducing number of gates in CSLA. Area and power dissipation in CSLA using BEC observed 17.4% and 15.4% reduction comparing with conventional CSLA i.e.…”

Section: Existing Workmentioning

confidence: 99%

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Design of Low-Power Reversible Carry Select Adder using D-Latch

Prasanth¹,

Anil²,

Sahithi³

et al. 2017

International Journal of Innovative Research in Electrical, Ele

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Most important design parameter in integrated circuit is Power dissipation after speed. Adders are one of the basic fundamental component in such circuit, designing much efficient Adder results in optimizing whole circuit. Due to rapid growth in technology there is a need of fast processing arithmetic unit, so Carry Select Adder (CSLA) is one of the fast processing adder. By observing the CSLA circuitry it is noticed that, further optimization can be achieved in various criteria. Power dissipation results only when bits are lost while processing, as per Launder"s principle, KTln2 heat is dissipated if there is any loss in bit. Since conventional CSLA is designed using irreversible logic gates which it results much more power dissipation but it can be overcome by employing reversible logic to reduce power dissipation till some extent. By using this idea, following paper proposes a efficient technique to design 8-bit CSLA using reversible logic, for this purpose this paper undertakes 8-bit CSLA with D Latch.. This paper evaluates the proposed design in-terms of power, delay, garbage output, quantum cost and number of gates using 90nm CMOS process technology for n-bits. All the works related to proposed design carried in cadence virtuoso tool and by comparing the simulation results and analysis this paper observed that, proposed reversible CSLA using D-latch attains low power dissipation which is equal to 74.1238uW,which shows decrease in 65.175%than irreversible CSLA using D-latch.

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Section: Existing Workmentioning

confidence: 99%

“…To design 3:3 RDF used three RDF where each designed using one F gate and two FG gate. To calculate NOG for n-bit proposed CSLA following equation deduced NOG n-bit = n/2NOG RRCA + (n-2)/2[NOG 3:3RDF +NOG 6 …”

Section: Number Of Gates (Nog)mentioning

confidence: 99%

Design of Low-Power Reversible Carry Select Adder using D-Latch

Prasanth¹,

Anil²,

Sahithi³

et al. 2017

International Journal of Innovative Research in Electrical, Ele

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show abstract

“…In this paper, we propose a novel full adder design featuring Complementary and Level Restoring Carry Logic (CLRCL). The goal is to reduce the circuit complexity and to achieve faster cascade operation [12].…”

Section: The Proposed Clrcl Full Adder Designmentioning

confidence: 99%

Comparative Analysis of 8-Bit Adder Cells Using CLRCL Full Adder Logic

Kumar¹,

Grover²,

Grover³

2014

GSTF J Comput

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Abstract-In this paper, we propose a modified low power 10-T Adder design usi ng 10 transist or s & 12 transist or s feat uring highe r computing speed, lower operating voltage, and lower energy consumption compared with peer designs. The simulation results, based on 0.18um process models, indicate that the proposed design has the lowest working Vdd and highest working frequency among all designs using 10 transistors & 12 transistors. It also features the lowest energy consumption per addition among these designs. In addition, the performance edge of the proposed design in both speed and energy consumption becomes even more significant as the word length of the adder increases. Index Terms-Complementary & Level Restoring Full Adder, Boolean Logic I. INTRODUCTIONT he essence of the digital computing lies in the full adder design. The design criteria of a full adder are usually multifold. Transistor count is, of course, a primary concern which largely affects the design complexity of many function units such as multiplier and ALU. Two other important yet often conflicted design criteria are power consumption and speed. A better metric would be the power delay product or energy consumption per operation to indicate the optimal design tradeoffs. Related to the power consumption is the lowest supply voltage the design can still operate properly. Numerous full adder designs [1][2][3][4][5][6] in the categories of fully static CMOS, dynamic circuit, transmission gate, or pass transistor logic have been presented. The full adder design in fully static CMOS is the most conventional one but requires as many as 28 transistors. Dynamic circuits can significantly reduce the transistor count but the incurred power consumption, including that of the clock tree, is usually high. Building logic in transmission gate is another alternative to reduce the circuit complexity. In [1], transmission gate plus inverter based full adder designs were presented using 20 and 16 transistors, respectively. To pursue even lower transistor count full adder designs, pass transistor logic can be used in lieu of transmission gate. In [2], pass transistor logic based XOR/XNOR circuits were used and the full adder design consists of only 14 transistors. Despite the saving in transistor count, the output voltage level is degraded at certain input combinations due to threshold voltage loss problem. At the cost of

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“…Another modified SQRT CSLA using BEC-1 and Selection unit. It reduces the area but slightly increasing the delay [4]. In both architecture conventional CSLA and modified SQRT CSLA area is increased when number of bit increases.…”

Section: Introductionmentioning

confidence: 99%

Implementation on FPGA Area-Delay Efficient Architecture of CSLA

e¹

2015

IJAREEIE

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ABSTRACT:In the design of VLSI, area and delay is play important role and the field of VLSI less delay and low area is required adder unit in data processing processor for performing fast arithmetic operation. Architecture of CSLA, there is chance to reduce area & delay which is based on sum generation unit and carry generation unit. In this paper 128bit, 64bit, 32bit, 16bit conventional CSLA, modified CSLA and Proposed CSLA architecture have been implemented on FPGA and compared result in term area that is of count of gate and delay. The proposed design has reduced area and delay. This work has showed the performance of the proposed design in term of delay and area. ISim simulator is used for simulating the CSLA and synthesized using Xilinx ISE design suit 14.7 then implementation is done on in virtex7 FPGA kit.

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Carry-select adder using single ripple-carry adder

Cited by 150 publications

References 1 publication

Design of Low-Power Reversible Carry Select Adder using D-Latch

Design of Low-Power Reversible Carry Select Adder using D-Latch

Comparative Analysis of 8-Bit Adder Cells Using CLRCL Full Adder Logic

Implementation on FPGA Area-Delay Efficient Architecture of CSLA

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