Cells reconfiguration around defects in CMOS/nanofabric circuits using simulated evolution heuristic

Arafeh, Abdalrahman M.; Sait, Sadiq M.

doi:10.1109/isqed.2015.7085492

Cited by 3 publications

(3 citation statements)

References 19 publications

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“…In such cases, resorting to SAT or sequential-attempts algorithms will be insufficient and circuit reconfiguration may fail. In this paper, we extend our previous work in [33]. We introduce a complete design flow for CMOL cells mapping and introduce a new type of defect.…”

Section: Literature Reviewmentioning

confidence: 91%

Reconfiguration-Based Defect-Tolerant Design Automation for Hybrid CMOS/Nanofabrics Circuits Using Evolutionary and Non-Deterministic Heuristics

Sait

Arafeh

2015

Arab J Sci Eng

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Recently, a shift from CMOS lithography to nanoelectronics chemical assembly has been under investigation. Nanoscale components are assembled into arrays of low-power and high-density nanofabrics, which can be integrated with conventional CMOS systems. The inability to achieve inexpensive defect-free mass manufacturing of nanoelectronics is the largest impediment of their adoption. Limited nanowire lengths and defect-prone nanodevices pose significant challenges for design automation tools. In this work, we propose a design phase for cell mapping and reconfiguration in novel hybrid CMOS/nanoelectronics architecture called CMOL. Reconfiguration consists of finding new suitable physical location for each gate such that the circuit becomes defect free. The novelty of this work is to engineer non-deterministic iterative search heuristics, namely simulated evolution (SimE) and Tabu search (TS), to find cell assignment around defective nano-components. Circuits of various sizes from ISCAS'89 benchmarks are used to evaluate the designed heuristics. Results show that SimE and TS yield successful reconfigurations in reasonable computation time when nanodevice defect rate is as high as 50 % and nanowire cut rate up to 70 %.

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Section: Literature Reviewmentioning

confidence: 91%

Reconfiguration-Based Defect-Tolerant Design Automation for Hybrid CMOS/Nanofabrics Circuits Using Evolutionary and Non-Deterministic Heuristics

Sait

Arafeh

2015

Arab J Sci Eng

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“…Inspired by the theory of evolution, the algorithm has several distinctive features as mentioned in Section 1. Despite its distinctive features and excellent performance, the algorithm and its hybrid variants have received little attention from researchers in some domains such as healthcare [31], internet traffic engineering [18], network design optimization [6,32], microelectronics [33][34][35], and cloud computing [17,36,37].…”

Section: Basic Simulated Evolution Algorithmmentioning

confidence: 99%

Adaptation of the simulated evolution algorithm for wind farm layout optimization

Khan¹

2022

FME Transactions

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Wind energy is a potential replacement for traditional, fossil-fuel-based power generation sources. One important factor in the process of wind energy generation is to design of the optimal layout of a wind farm to harness maximum energy. This layout optimization is a complex, NP-hard optimization problem. Due to the sheer complexity of this layout design, intelligent algorithms, such as the ones from the domain of natural computing, are required. One such effective algorithm is the simulated evolution (SE) algorithm. This paper presents a simulated evolution algorithm engineered to solve the wind farm layout design (WFLD)optimization problem. In contrast to many non-deterministic algorithms, such as genetic algorithms and particle swarm optimization which operate on a population, the SE algorithm operates on a single solution, decreasing the computational time. Furthermore, the SE algorithm has only one parameter to tune as opposed to many algorithms that require tuning multiple parameters. A preliminary empirical study is done using data collected from a potential location in the northern region of Saudi Arabia. Experiments are carried out on a 10 × 10 grid with 15 and 20 turbines while considering turbines with a rated capacity of 1.5 MW. Results indicate that a simulated evolution algorithm is a viable option for the said problem.

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“…Though the density advantage is significant, the nanodevice utilization in the previously reported works on CMOL FPGAs [19], [21], [23], [26]- [30] is well below 1% due to the limited benefits of utilizing high fan-in gates. In this paper, we present a modification to the original logic structure [19], [20] and show that some information processing tasks are uniquely suited for the high fan-in gates of CMOL FPGA circuits.…”

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confidence: 99%

High-Throughput Pattern Matching With CMOL FPGA Circuits: Case for Logic-in-Memory Computing

Madhavan

Sherwood

Strukov

2018

IEEE Trans. VLSI Syst.

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In this paper, we propose a novel CMOS+ MOLecular (CMOL) field-programmable gate array (FPGA) circuit architecture to perform massively parallel, high-throughput computations, which is especially useful for pattern matching tasks and multidimensional associative searches. In the new architecture, patterns are stored as resistive states of emerging nonvolatile memory nanodevices, while the analyzed data are streamed via CMOS subsystem. The main improvements over prior work offered by the proposed circuits are increased nanodevice utilization and, as a result, substantially higher throughput, which is demonstrated by a detailed analysis of the implementation of pattern matching task on the new architecture. For example, our estimates show that the proposed CMOL FPGA circuits based on the 22-nm CMOS technology and one crossbar layer with 22-nm nanowire half-pitch allows up to 12.5% average nanodevice utilization, i.e., the fraction of the devices turned to the high conductive state, as compared to a typical ∼0.1% of the original CMOL FPGA circuits. This in turn enables throughput close to 7.1 × 10 16 bits/s/cm 2 at ∼ 1 fJ/bit energy efficiency, for matching of ∼ 10 7 250-bit patterns stored locally on a 1 cm 2 chip. These numbers are at least 2 orders of magnitude better throughput as compared to that of other state-of-the-art FPGA methods, and begin to approach ternary content-addressable memory-like performance at similar CMOS technology nodes. More generally, we argue that the proposed concept combines the versatility of reconfigurable architectures and density of the associative memories. It can be viewed as a very tight symbiotic integration of memory and logic functions for high-performance logic-in-memory computing. Index Terms-CMOS+MOLecular (CMOL), fieldprogrammable gate array (FPGA), hybrid circuits, logicin-memory computing, memristor, pattern matching, ReRAM, resistive switching, ternary content-addressable memory (TCAM). I. INTRODUCTION R ECONFIGURABLE circuits (RCs) are very efficient for information processing tasks [1], such as image and signal processing (e.g., filtering, edge detection, coding, and

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Cells reconfiguration around defects in CMOS/nanofabric circuits using simulated evolution heuristic

Cited by 3 publications

References 19 publications

Reconfiguration-Based Defect-Tolerant Design Automation for Hybrid CMOS/Nanofabrics Circuits Using Evolutionary and Non-Deterministic Heuristics

Reconfiguration-Based Defect-Tolerant Design Automation for Hybrid CMOS/Nanofabrics Circuits Using Evolutionary and Non-Deterministic Heuristics

Adaptation of the simulated evolution algorithm for wind farm layout optimization

High-Throughput Pattern Matching With CMOL FPGA Circuits: Case for Logic-in-Memory Computing

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