Characterization of recessed Ohmic contacts to AlGaN/GaN

Abstract

In this work the choice of appropriate test structures and characterization methods for recessed Ohmic contacts to AIGaN/GaN is discussed. It is shown that, in the worst case scenario, the prevailing assumption of identical sheet resistance between and under the contacts can lead to errors of up to 3000 % in the extracted specific contact resistance.

Optimization of Ohmic Contact for AlGaN/GaN HEMT on Low-Resistivity Silicon

“…In below channel etching, we find that non-planar ohmic surface performed much better than the planar surface, extra filling of Ti metal in the etched area did not show any significant improvement in the contact resistance. Previous some research [9] [14] has shown etching below the 2DEG channel, in the case of a single recess ohmic contact, to exhibit high contact resistance. Even though the barrier height is low, the absence of 2DEG channel underneath the contact limits carrier tunneling to a smaller region around the sidewall of the recessed barrier.…”

“…Ti/Al based metal schemes like Ti/Al/Ni/Au, Ti/Al/Mo/Au, Ta/Ti/Al/Ni/Au, Ti/Al/Ta/Au and Ti/Al/Ti/TiN annealed at elevated temperatures have been successfully demonstrated to reduce contact resistance [3] [4] [5] [6] [7]. Recess of the barrier layer at the drain and source has also proven to be successful [8] [9]. Regrowth of N-type GaN is so far the most effective way to reduce ohmic contact resistance, however the procedure is currently cost prohibitive and adds significant complexity to the fabrication process.…”

Improvement of AlGaN/GaN High-Electron-Mobility Transistor Radio Frequency Performance Using Ohmic Etching Patterns for Ka-Band Applications

“…The OEPs were etched to around 10 nm above the 2-dimensional-electron-gas (2DEG) channel, which etch-stopped at the AlGaN barrier layer. The recessed depths were chosen only above 2DEG, due to the higher contact resistances measured for the devices with recessed depth below 2DEG, as shown in previous research [ 28 ]. After wafer cleaning with a diluted hydrochloric acid (HCl) solution to remove the native oxide layer [ 29 ], an ohmic metal stack of Ti/Al/Ni/Au was deposited with the e-beam evaporation system (E-gun) and annealed by the rapid thermal annealing system (RTA) at 850 °C for 30 s in N 2 ambient.…”

RESURF power semiconductor devices : performance and operating limits

“…At present time, there is plenty of research activity in both industry and academia [86] aimed at manufacturing reliable GaN power devices. Issues related to current collapse [87,88] and optimization of the metal contacts [89] are gradually being solved and the costs of the manufacturing process have been significantly reduced. As suggested in [90], it is expected that GaN transistors will dominate the market of discrete power devices in the near future (GaN is ready to fire!).…”