Charge sensing properties of monolithic CMOS pixel sensors fabricated in a 65 nm technology

Bugiel, S.; Dorokhov, A.; Aresti, M.; Baudot, J.; Beolè, S.; Besson, Auguste; Bugiel, Roma; Cecconi, Leonardo; Colledani, C.; Deng, W.; Mauro, A. Di; Bitar, Ziad El; Goffe, Mathieu; Hasenbichler, Jan Anton; Hong, Geun Hee; Hu-Guo, Christine; Jaaskelainen, Kimmo; Kluge, A.; Mager, M.; Marras, D.; Mélo, João de; Münker, Magdalena; Pham, Hūng Viêt; Piro, F.; Reidt, F.; Rinella, G. Aglieri; Russo, R.; Sarritzu, Valerio; Senyukov, S.; Snoeys, W.; Šuljić, M.; Usai, G. L.; Valin, Isabelle; Winter, M.; Wu, Yitao

doi:10.1016/j.nima.2022.167213

Cited by 6 publications

(4 citation statements)

References 2 publications

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“…The MLR1 test system has been employed in an extensive campaign to validate and characterize the pixel properties both in the laboratory and beam tests [5]. As an example, figures 3 and 4 show preliminary results from lab tests on two MLR1 chips operated and read out by the MLR1 test system.…”

Section: Tests and Preliminary Resultsmentioning

confidence: 99%

A readout system for monolithic pixel sensor prototypes towards the upgrade of the ALICE Inner Tracking System

Sarritzu

2023

J. Inst.

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The ALICE experiment at CERN is developing an innovative third iteration of the three innermost layers of the Inner Tracking System (ITS3) to be installed during the Long Shutdown 3 of the LHC (2026–28) [1]. Based on a commercial 65 nm CMOS imaging technology by TowerJazz [2], it consists of truly cylindrical wafer-scale sensors that can be installed as close as 18 mm to the interaction point. In order to validate the technology, several test chips were produced in a first submission named Multi-Layer Reticle 1 (MLR1). This contribution will describe the development, features, and performance of a custom test system for some of the prototypes in MLR1, namely Analogue and Digital Pixel Test Structures (APTS and DPTS, respectively) and pixel matrices with rolling shutter readout (CE65).

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Section: Tests and Preliminary Resultsmentioning

confidence: 99%

A readout system for monolithic pixel sensor prototypes towards the upgrade of the ALICE Inner Tracking System

Sarritzu

2023

J. Inst.

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“…The main goal of the APTS is to explore different pixel designs. The CE65 [8] features a 64×32 pixel matrix with a pixel pitch of 15 µm or a 48×32 pixel matrix with a pixel pitch of 25 µm. Its readout is based on a rolling shutter architecture with 50 µs integration time.…”

Section: Pos(vertex2023)046mentioning

confidence: 99%

Recent results from MAPS prototypes for ITS3

Villani

2024

Proceedings of the 32nd International Workshop on Vertex Detectors — PoS(VERTEX2023)

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The present Inner Tracking System (ITS2) of the ALICE Experiment will be upgraded during the LHC Long Shutdown 3 (LS3). The upgrade foresees the replacement of the three innermost layers with a truly cylindrical vertex detector, the ITS3. Such tracker will be composed of two half barrels, comprising three self-supporting cylindrical half-layers, each made of two large-area (O(10×26 cm 2 )) ultra-thin (≤50 µm) bent stitched Monolithic Active Pixel silicon Sensors (MAPS) fabricated in a 65 nm CMOS process. This novel technology will allow for an unprecedented low material budget of 0.05 %X/X 0 per layer, strongly improving the tracking efficiency and the pointing resolution, especially for low-momentum particles. An extensive campaign to validate the sensor technology through characterisation both in the laboratory and with in-beam measurements is ongoing. For this purpose, multiple test structures were included in the first test production (MLR1) to be tested: Analog Pixel Test Structure (APTS), Circuit Exploratoire 65 (CE65) and Digital Pixel Test Structure (DPTS). Excellent performance in terms of detection efficiency (>99%), spatial resolution (3-4 µm) and response to X-rays were achieved. Moreover, good performance achieved on irradiated APTS and DPTS proved the 65 nm CMOS process tolerant far beyond 1×10 13 1 MeV n 𝑒𝑞 cm −2 (NIEL) and 10 kGy (TID), expected for the ALICE ITS3 operating environment. This contribution will describe the different test structure flavours and the most recent results from laboratory and beam test measurements will be presented.

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“…The digital pixel test structure or DPTS [18] contains a 32 by 32 pixel matrix at 15 𝜇m pitch with an amplifier and discriminator in each pixel and a time encoded digital readout. The CE65 contains a pixel matrix with analog readout in a rolling shutter configuration [19,20]. Figure 11 shows the spectrum of the charge collected on the seed pixel from a 55 Fe radioactive source for different pixel variants and process splits.…”

Section: Pos(pixel2022)083mentioning

confidence: 99%

Optimization of a 65 nm CMOS imaging process for monolithic CMOS sensors for high energy physics

Snoeys¹,

Rinella²,

Andronic³

et al. 2023

Proceedings of 10th International Workshop on Semiconductor Pixel Detectors for Particles and Imaging — PoS(Pixel2022)

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Charge sensing properties of monolithic CMOS pixel sensors fabricated in a 65 nm technology

Cited by 6 publications

References 2 publications

A readout system for monolithic pixel sensor prototypes towards the upgrade of the ALICE Inner Tracking System

A readout system for monolithic pixel sensor prototypes towards the upgrade of the ALICE Inner Tracking System

Recent results from MAPS prototypes for ITS3

Optimization of a 65 nm CMOS imaging process for monolithic CMOS sensors for high energy physics

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