Chip Multithreading: Opportunities and Challenges

Abstract

Chip Multi-Threaded (CMT) processors provide support for many simultaneous hardware threads of execution in various ways, including Simultaneous Multithreading (SMT) and Chip Multiprocessing (CMP). CMT processors are especially suited to server workloads, which generally have high levels of ThreadLevel Parallelism (TLP). In this paper, we describe the evolution of CMT chips in industry and highlight the pervasiveness of CMT designs in upcoming general-purpose processors. The CMT design space accommodates a range of designs between the extremes represented by the SMT and CMP designs and a variety of attractive design options are currently unexplored. Though there has been extensive research on utilizing multiple hardware threads to speed up single-threaded applications via speculative parallelization, there are many challenges in designing CMT processors, even when sufficient TLP is present. This paper describes some of these challenges including, hot sets, hot banks, speculative prefetching strategies, request prioritization and off-chip bandwidth reduction.

High Throughput Parallelization of AES-CTR Algorithm

“…As a Chip MultiProcessor (CMP), it can execute multiple software threads on a single chip at the same time. Thus a multi-core processor provides a larger capacity of computations performed per chip for a given time interval (or throughput) [19]. All of the CPU vendors including Intel, AMD, IBM, Oracle/Sun, among others have introduced the multi-core processors to the market.…”

“…Software processes or threads running on the cores/threads of the same processor chip compete for the shared resources, which can cause conflicts and hurt perfor-mance. Thus efficiently utilizing the multi-core processors is a challenging task [19].…”

“…As a Chip MultiProcessor (CMP), a multi-core processor can execute multiple software threads on a single chip at the same time. Thus it can provide higher computing power per chip for a given time interval (or throughput) [19]. The multi-core design trend has also appeared in the recent Graphic Processing Unit (GPU) by incorporating Shader, Vertex, Pixel unitsseparate processing units in the earlier GPUs-into uniform programmable processing units or cores [15].…”

Conserving Memory Bandwidth in Chip Multiprocessors with Runahead Execution

“…For many commercial applications with an abundance of thread-level parallelism [25], adding cores or threads yields a very appealing performance improvement per mm 2 . The number of cores per chip will likely be scaled up as high as the chip power and bandwidth will support.…”

A Unified Framework for System-Level Design: Modeling and Performance Optimization of Scalable Networking Systems

“…Typical scalable networking systems such as Ethernet controllers and switches have particularly tight time-to-market requirement, which requires a highly efficient design cycle. The design of reliable, low-energy, and high performance systems is best accomplished when the system modeling is done with careful consideration of the performance constraints [3].…”