Circuit-Level Techniques for Logic and Memory Blocks in Approximate Computing Systemsx

Amanollahi, Saba; Kamal, Mehdi; Afzali-Kusha, Ali; Pedram, Massoud

doi:10.1109/jproc.2020.3020792

Cited by 21 publications

(7 citation statements)

References 113 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Moore's law governs Moore's law governs more than Moore, above and beyond Moore, allowing non-Si CMOS devices to scale IC performance and directing compact systems [5], [6]. Low power consumption and minimal latency are the goals of integrated circuit (IC) design for logic and memory devices [7]. Technology scalability increases performance but has drawbacks as well [8], [9], [10].…”

Section: Figure 1 Moore's Law Applied To Technology Trendmentioning

confidence: 99%

Analytical Modelling and Performance Characterization of Hybrid SET-MOS

Shruti Suman

2024

jes

View full text Add to dashboard Cite

Gordon Moore's "Moore's Law" suggests chip functionality demand doubles every 1.5-2 years, with global semiconductor technology roadmap recommending sub-nanometer ranges for IC production in nano-electronics. The single electron transistor (SET) is a promising nano-scale device that can be co-integrated with CMOS technology to improve performance. The paper explores the tunnelling effect between nanoparticles in single electron transistors (SET), revealing coulomb blockade transactions and resistance increases with reduced bias. It focuses on single electron transistors and pre-terminal devices, discussing IV characteristics, coulomb diamond plots, and metallic quantum dots. This research also explores the hybrid SET-FET based model, focusing on developing a room temperature SET in CMOS comparable technology with a Field Effect Transistor (FET). Prediction models and exploratory studies guide the integration of SET-FET technology. SIMON is a comprehensive simulator designed for single-electron devices and circuits. The output current is not impacted by capacitances up to 1 pF, and FET size in the micron range are appropriate for SET signal amplification up to 4 µA. This research explores the modelling of SET-FET technology in highlighting its ability to mitigate drawbacks in low drive current when combined with a FET. It also explores device variability mitigation in nanoscale array configurations, finding that SET-FET significantly reduces variability in larger arrays, despite the impact of capacitance and resistance.

show abstract

Section: Figure 1 Moore's Law Applied To Technology Trendmentioning

confidence: 99%

Analytical Modelling and Performance Characterization of Hybrid SET-MOS

Shruti Suman

2024

jes

View full text Add to dashboard Cite

show abstract

“…Bui, et al [61] exploits the delay of the score signal for a Hamming distance search CAM. A small Hamming distance tolerance (≤ 2 bits) approximate CAM is proposed in [62], [63]. Garzón, et al [34] and Hanhan, et al [35] use the combination of the voltage, controlling the speed of the matchline discharge, and the sense amplifier reference voltage to define the Hamming distance threshold.…”

Section: Related Workmentioning

confidence: 99%

AM⁴: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing

Garzón

Lanuzza

Teman

et al. 2023

IEEE J. Emerg. Sel. Topics Circuits Syst.

View full text Add to dashboard Cite

In-memory computing seeks to minimize data movement and alleviate the memory wall by computing in-situ, in the same place that the data is located. One of the key emerging technologies that promises to enable such computing-inmemory is spin-transfer torque magnetic tunnel junction (STT-MTJ). This paper proposes AM 4 , a combined STT-MTJ-based Content Addressable Memory (CAM), Ternary CAM (TCAM), approximate matching (similarity search) CAM (ACAM), and in-memory Associative Processor (AP) design, inspired by the recently announced Samsung MRAM crossbar. We demonstrate and evaluate the performance and energy-efficiency of the AM 4based AP using a variety of data intensive workloads. We show that an AM 4 -based AP outperforms state-of-the-art solutions both in performance (with the average speedup of about 10 ×) and energy-efficiency (by about 60 × on average).

show abstract

“…In this design, the delay of the score signal is proportional to the Hamming distance between the search and stored patterns. In the approximate search enabled CAM for energy efficient GPUs, proposed in [16], [53], a small Hamming distance (≤ 2 bits) is tolerated through meticulous timing of the matchline discharge. In [17], Hamming distance of (≤ 4 bits) is tolerated by using delay lines at the clock inputs of four separate sense amplifiers on each matchline.…”

Section: B Approximate Content-addressable Memorymentioning

confidence: 99%

Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification

et al. 2022

View full text Add to dashboard Cite

This paper proposes a novel Hamming distance tolerant content-addressable memory (HD-CAM) for energy-efficient in-memory approximate matching applications. HD-CAM exploits NOR-type based static associative memory bitcells, where we add circuitry to enable approximate search with programmable tolerance. HD-CAM implements approximate search using matchline charge redistribution rather than its rise or fall time, frequently employed in state-of-the-art solutions. HD-CAM was designed in a 65 nm 1.2 V CMOS technology and evaluated through extensive Monte Carlo simulations. Our analysis shows that HD-CAM supports robust operation under significant process variations and changes in the design parameters, enabling a wide range of mismatch threshold (tolerable Hamming distance) levels and pattern lengths. HD-CAM was functionally evaluated for virus DNA classification, which makes HD-CAM suitable for hardware acceleration of genomic surveillance of viral outbreaks, such as Covid-19 pandemics.

show abstract

Circuit-Level Techniques for Logic and Memory Blocks in Approximate Computing Systemsx

Cited by 21 publications

References 113 publications

Analytical Modelling and Performance Characterization of Hybrid SET-MOS

Analytical Modelling and Performance Characterization of Hybrid SET-MOS

AM⁴: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing

Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification

Contact Info

Product

Resources

About

Circuit-Level Techniques for Logic and Memory Blocks in Approximate Computing Systemsx

Cited by 21 publications

References 113 publications

Analytical Modelling and Performance Characterization of Hybrid SET-MOS

Analytical Modelling and Performance Characterization of Hybrid SET-MOS

AM4: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing

Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification

Contact Info

Product

Resources

About

AM⁴: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing