CMOS Reliability From Past to Future: A Survey of Requirements, Trends, and Prediction Methods

Hill, Ian E. J.; Chanawala, Parvez A.; Singh, Rohit K; Sheikholeslam, S. Arash; Ivanov, A.

doi:10.1109/tdmr.2021.3131345

Cited by 18 publications

(12 citation statements)

References 136 publications

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“…Combatting counterfeiting through recycling requires identifying circuits which have begun to age but still operate within specifications. CMOS integrated circuits (ICs) are all affected by aging mechanisms which degrade their performance with use [4]. Eventually this degradation is significant enough that an aged circuit can no longer operate within specifications.…”

Section: Introductionmentioning

confidence: 99%

Leveraging Public Information to Fit a Compact Hot Carrier Injection Model to a Target Technology

2023

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The design of countermeasures against integrated circuit counterfeit recycling requires the ability to simulate aging in CMOS devices. Electronic design automation tools commonly provide this ability; however, their models must be tuned for use with a specific target technology. This requires data which is ideally provided by a fab. It may also be collected from a set of purpose-built test devices, a costly and time-consuming process. Here we describe a novel, low-cost, and rapid approach to tuning such models. Our iterative method leverages public domain data sourced from published studies to fit an aging model. Results are statistically validated against the target technology's specification. We demonstrate our approach by fitting a compact hot carrier injection degradation model for use with both core and I/O nMOSFETs from a specific 65 nm technology. Our resulting model parameter values are validated with a maximum error of 0.5 % with a 99 % confidence bound.

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Section: Introductionmentioning

confidence: 99%

Leveraging Public Information to Fit a Compact Hot Carrier Injection Model to a Target Technology

2023

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“…With the development of semiconductor technology, chips are widely used in various fields. Unlike consumer electronics, cost reduction is often the primary consideration in the design process, and chip reliability requirements in some new areas are more important, such as automotive, medical, aerospace, and so on [ 1 , 2 ].…”

Section: Introductionmentioning

confidence: 99%

Study on ESD Protection Circuit by TCAD Simulation and TLP Experiment

Chai

Liu

et al. 2023

Micromachines

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The anti-ESD characteristic of the electronic system is paid more and more attention. Moreover, the on-chip electrostatic discharge (ESD) is necessary for integrated circuits to prevent ESD failures. In this paper, the mixed TCAD model of the ESD protection circuit is built and simulated, and the negative transmission line pulse (TLP) injection damage experiment is carried out on the CD4069UBC chip. The circuit model consists of three-dimensional shallow trench isolation (STI) diode TCAD models and a three-dimensional multi-gate Complementary Metal-Oxide-Semiconductor (CMOS) inverter TCAD model. Moreover, the TCAD modeling is based on a 0.25 μm technology node. Through the transient simulation of the electrothermal coupling, the electrical signal of the input and output nodes of the circuit and the distribution of the electrothermal parameters in the device are obtained. Moreover, by analyzing the simulation results, the physical phenomena and the mechanisms of interference and damage mechanism during TLP injection are explained. The location and type of diode damage in the TLP injection simulation results of the circuit model are consistent with the TLP experiment damage results. The proposed ESD protection circuit model and analysis method are beneficial to ESD robustness prediction and ESD soft damage analysis of IC.

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“…7 The possibility of employing complementary logic configurations (CMOS) allows a more efficient design of logic elements, which are faster and more robust, consume less power and have an overall smaller footprint than similar circuits obtained from unipolar materials. 8,9 The possibility of using complementary schemes is not straightforward with organic semiconductors. 10,11 One of the most critical limitations concerns the difficulty in locally confining the doping process.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Preparation of different conjugated polymers characterized by complementary electronic properties from an identical precursor

Carlotti,

Losi,

De Boni

et al. 2023

Polym. Chem.

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CMOS Reliability From Past to Future: A Survey of Requirements, Trends, and Prediction Methods

Cited by 18 publications

References 136 publications

Leveraging Public Information to Fit a Compact Hot Carrier Injection Model to a Target Technology

Leveraging Public Information to Fit a Compact Hot Carrier Injection Model to a Target Technology

Study on ESD Protection Circuit by TCAD Simulation and TLP Experiment

Preparation of different conjugated polymers characterized by complementary electronic properties from an identical precursor

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