CMOS X-Ray Detector With Column-Parallel 14.3-bit Extended-Counting ADCs

Shin, Min-Seok; Kim, Jong-Boo; Jo, Yun-Rae; Kim, M.; Kwak, Bong-Choon; Seol, Hyeon-Cheon; Kwon, Oh‐Kyong

doi:10.1109/ted.2013.2238674

Cited by 20 publications

(5 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…13(b) is given by (9) where is an integer from to . When , can be negligible and is expressed as (10) where (11) In (10), the first term of is the residue voltage without parasitic capacitance as described in Section III-B and the second term of represents the error caused by parasitic capacitance. Fig.…”

Section: Effect Of Parasitic Capacitance During Two-step Operationmentioning

confidence: 99%

“…The proposed ADC generates a 12-bit output data by using 6-bit embedded SA ADC with an adjustable . To eliminate the pixel noise and offset of the readout circuit, a digital correlated double sampling is adopted [9]- [11]. The row driver which generates the pixel control signal is arranged in the vertical direction of the pixel array.…”

Section: Sensor Architecturementioning

confidence: 99%

See 1 more Smart Citation

A Multi-Bit Incremental ADC Based on Successive Approximation for Low Noise and High Resolution Column-Parallel Readout Circuits

Hong

Kwon

2015

IEEE Trans. Circuits Syst. I

Self Cite

View full text Add to dashboard Cite

This paper proposes a multi-bit incremental analog-to-digital converter (ADC) based on successive approximation (SA) for column-parallel readout circuits. The proposed ADC suppresses the random noise and enhances the resolution by embedding the conventional SA ADC with an integrator and decimation filter. In addition, the operating speed is increased through the two-step operations of coarse conversion with the proposed ADC and fine conversion with the embedded SA ADC. A residue fitting method is adopted to adjust the residue voltage to the fine conversion range after the coarse conversion. The proposed ADC with 12-bit resolution was fabricated using a 0.13 CMOS image sensor process with a pixel array that has an image format of 648 488 and a pixel size of . The measured results show a random noise of 108 , a dynamic range of 60.9 dB, a differential nonlinearity of 1.02/ 0.34 least significant bit (LSB), and an integral nonlinearity of 0.64/ 0.54 LSB.Index Terms-Column-parallel readout, incremental analog-todigital converter (ADC), successive approximation.

show abstract

Section: Effect Of Parasitic Capacitance During Two-step Operationmentioning

confidence: 99%

Section: Sensor Architecturementioning

confidence: 99%

A Multi-Bit Incremental ADC Based on Successive Approximation for Low Noise and High Resolution Column-Parallel Readout Circuits

Hong

Kwon

2015

IEEE Trans. Circuits Syst. I

Self Cite

View full text Add to dashboard Cite

show abstract

“…For example, Seo et al [9] have developed a 17-bit IΣ ∆ + cyclic ADC, and Shin et al [10] introduced a 14.3-bits IΣ ∆ +SAR ADC, both focusing imaging systems. However, these architectures still require moderately complex circuitry due to the use of Nyquist converters in one of the steps.…”

Section: Introductionmentioning

confidence: 99%

A 14-bit 250 kS/s two-step inverter-based incremental $$\varSigma \varDelta$$ Σ Δ ADC for CMOS image sensor in $$0.18\,\upmu \hbox {m}$$

Bisiaux

Lelandais-Perrault

Kolar

et al. 2018

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

This paper presents a 14-bit Incremental Sigma Delta analog-to-digital converter suitable for column wise integration in a CMOS image sensor. A two step conversion is performed to improve the conversion speed. As the same Σ ∆ modulator is used for both steps, the overall complexity is reduced. Furthermore, the use of inverter-based amplifiers instead of operational transconductance amplifier facilitates the integration within the column pitch and decreases power consumption. MonteCarlo simulations have been done in order to validate the design of the inverter. The proposed ADC is designed in 0.18 µm CMOS technology. The simulation shows that for a 1.8 V voltage supply, a 20 MHz clock frequency and an oversampling ratio (OSR) of 70, the power consumption is 460 µW, achieving an SNDR of 85.4 dB. Keywords ADC • incremental • sigma-delta • CMOS Image Sensor • column-parallel • inverter-based

show abstract

“…For example, Seo et al [1] have developed a 17 bits IΣ∆+cyclic ADC, and Shin et al [2] introduced a 14.3-bits IΣ∆+SAR ADC, both focusing imaging systems. However, these architectures still required moderately complex circuitry due to the use of Nyquist converters in one of the steps.…”

Section: Introductionmentioning

confidence: 99%

A 14-b two-step inverter-based ΣΔ ADC for CMOS image sensor

Bisiaux

Lelandais-Perrault

Kolar

et al. 2017

2017 15th IEEE International New Circuits and Systems Conference (NEWCAS)

View full text Add to dashboard Cite

This paper presents a 14-bit Incremental Sigma Delta (IΣ∆) analog-to-digital converter (ADC) suitable for a column wise integration in a CMOS image sensor. A two-step conversion is performed to improve the conversion speed. As the same Σ∆ modulator is used for both steps, the overall complexity is reduced. Furthermore, the use of inverter-based amplifiers instead of operational transconductance amplifier (OTA) facilitates the integration within the column pitch and decreases power consumption. The proposed ADC is designed in 0.18 µm CMOS technology. The simulation shows that for a 1.8 V voltage supply, a 20 MHz clock frequency and an oversampling ratio (OSR) of 70, the power consumption is 460 µW, achieving an SNR of 83.7 dB.

show abstract

CMOS X-Ray Detector With Column-Parallel 14.3-bit Extended-Counting ADCs

Cited by 20 publications

References 17 publications

A Multi-Bit Incremental ADC Based on Successive Approximation for Low Noise and High Resolution Column-Parallel Readout Circuits

A Multi-Bit Incremental ADC Based on Successive Approximation for Low Noise and High Resolution Column-Parallel Readout Circuits

A 14-bit 250 kS/s two-step inverter-based incremental $$\varSigma \varDelta$$ Σ Δ ADC for CMOS image sensor in $$0.18\,\upmu \hbox {m}$$

A 14-b two-step inverter-based ΣΔ ADC for CMOS image sensor

Contact Info

Product

Resources

About