Coarse‐grained reconfiguration: dataflow‐based power management

Abstract

Power reduction in modern embedded systems design is a challenging issue exacerbated by the complexity and heterogeneity of their architecture. In the field of Reconfigurable Video Coding (RVC), to challenge these issues and cut-down time to market, dataflow-based techniques have been adopted. In particular, to master management and composability of dynamically reconfigurable systems, the authors have developed the multi-dataflow composer. Nevertheless, despite the RVC offers several different tools, in its reference design framework power management is still an open issue. To make some steps forward towards filling this gap, in this study, they address power management for coarse-grained reconfigurable systems combining structural and dynamic strategies, both to be applied at the dataflow level. © The Institution of Engineering and Technology 2015

Automatic generation of dataflow-based reconfigurable co-processing units

“…For the time being, the MDC-based design flow is under evaluation in a multi-decoder scenario [16], testing also a dedicated low-power extensions [30]. It would be useful to access also the proposed accelerator oriented extension in that context.…”

Automated power gating methodology for dataflow-based reconfigurable systems

“…In this paper, we are going to exploit some recent studies in the MPEG-RVC field related to clock gating over reconfigurable platforms [12] and we are going to present how to extend them to provide also power gating. These studies are related to the Multi-Dataflow Composer (MDC) tool, which is a RVC-CAL compliant framework conceived for the automatic creation and management of multi-functional systems.…”

“…MDC already embeds a power saving automatic feature [12]. In particular, it is able to analyse the input dataflow models and to extract from them the optimal actors partitioning in order to implement clock gating power management strategies.…”

“…In this work we have extended the results of [12] with a coarse-grained approach to power gating (PG). This technique switches off the power supply of the design portions that are not involved in the current computation.…”

“…This latter is then used to automatically derive a power gated system description. The proposed automated methodology has been tested, as a proof of concept, on an ASIC 90 nm CMOS technology and compared with another automatic power aware design flow [12]. Results revealed the potentiality of the proposed approach and gave us several hints for future optimizations.…”