Coding scheme for 3D vertical flash memory

Kim, Yongjune; Mateescu, Robert; Song, Sang-Bin; Bandić, Zvonimir; Kumar, B. V. K. Vijaya

doi:10.1109/icc.2015.7248332

Cited by 14 publications

(8 citation statements)

References 24 publications

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“…They also proposed to track the optimum read reference voltage for 3D NAND using three read operations. Another prior work [20] proposed to tackle fast-drift by enhancing the data encoding process based on sideinformation. While the annealing process does not treat shallow-trapped electrons, it can still be used orthogonally with our ERR scheme.…”

Section: Related Workmentioning

confidence: 99%

ReveNAND

Shihab¹,

Zhang

Kandemir

2018

ACM Trans. Archit. Code Optim.

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The paradigm shift from planar (two dimensional (2D)) to vertical (three-dimensional (3D)) models has placed the NAND flash technology on the verge of a design evolution that can handle the demands of next-generation storage applications. However, it also introduces challenges that may obstruct the realization of such 3D NAND flash. Specifically, we observed that the fast threshold drift (fast-drift) in a charge-trap flash-based 3D NAND cell can make it lose a critical fraction of the stored charge relatively soon after programming and generate errors. In this work, we first present an elastic read reference (V Ref) scheme (ERR) for reducing such errors in ReveNAND-our fast-drift aware 3D NAND design. To address the inherent limitation of the adaptive V Ref , we introduce a new intra-block page organization (hitch-hike) that can enable stronger error correction for the error-prone pages. In addition, we propose a novel reinforcement-learning-based smart data refill scheme (iRefill) to counter the impact of fast-drift with minimum performance and hardware overhead. Finally, we present the first analytic model to characterize fast-drift and evaluate its system-level impact. Our results show that, compared to conventional 3D NAND design, our ReveNAND can reduce fast-drift errors by 87%, on average, and can lower the ECC latency and energy overheads by 13× and 10×, respectively.

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Section: Related Workmentioning

confidence: 99%

ReveNAND

Shihab¹,

Zhang

Kandemir

2018

ACM Trans. Archit. Code Optim.

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“…Both architectures have a physically large cell size (indicated with the feature process size F process ), mainly due to a channel width wider than planar devices, although offering a smaller equivalent area occupation due to the stacking of multiple tiers [21,22]. The former solution does not offer any advantage over conventional planar CT cells in terms of P/E and retention, whereas the latter allows improving the cells programming performance, compared to planar devices, thanks to the shape of the CT cell, also known as Gate-All-Around (GAA) [23,24]. Nevertheless, 3D NAND memories face new reliability issues because of the cylindrical shape and the multi-layer stacking.…”

Section: Threshold Voltage Shift During Sensingmentioning

confidence: 99%

“…The 3D vertical flash memory has a nitride layer inside an Oxide-NitrideOxide (ONO) stack, which acts as a CT layer along the circumference of the thin poly-silicon vertical channel. Please note that each CT cell in this 3D vertical NAND memory is surrounded by the metal gates [24].…”

Section: Threshold Voltage Shift During Sensingmentioning

confidence: 99%

Reliability of 3D NAND Flash Memories

2016

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In this chapter the main reliability mechanisms affecting 3D NAND memories will be addressed, providing a comparison between 3D FG and 3D CT devices in terms of reliability and expected performances. Starting from an analysis of basic reliability issues related to both physical and architectural aspects affecting NAND memories, the specific physical mechanisms impacting the reliability of 2D CT NAND will be addressed. Then, a review of the main problems experimentally observed in different 3D CT cell concepts is reported. Finally, 3D FG memory concept is briefly introduced in order to understand the related reliability implications, and a comparison between 3D CT and 3D FG arrays is provided in terms of reliability and expected performances

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“…Consequently, the retrieved signal suffers from the inter-cell interference (ICI) due to the intensified coupling between neighboring cells, as well as other channel impairments [9], [10], [11]. To alleviate the ICI effect, channel signal processing schemes accounting the cell-to-cell interference are investigated such as soft information extraction scheme [12], [13] and coding with side information [14], which showed potential error rate performance improvement. In addition, various quantization schemes for NAND flash are suggested [15], [16], where the resolution of readback signal or the threshold voltage of the cell is limited by the number of read operations, while the programmed and erased voltage distributions are asymmetric.…”

Section: Introductionmentioning

confidence: 99%

Advanced channel signal processing for multi-track or multi-wordline data storage systems

Hwang

2015

2015 International Conference on Information and Communication Technology Convergence (ICTC)

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In this paper, advanced channel signal processing schemes are proposed for multi-track or multi-wordline read architecture in the future hard disk drive and NAND flash memory systems. As the capacity increases with aggressive scaling of the data bit or memory cell, the interference or coupling between neighboring information causes severe inter-track (ITI) or intercell interference (ICI), and advanced signal processing accounting the neighboring tracks or wordlines is needed to alleviate the effect of these interference. In magnetic recording (MR), arrayreader-based MR (ARMR) technology has shown a potential gain in the areal density capability (ADC) and the data transfer rate by employing multi-track channel signal processing, however skew effect causes complications in reliable data retrieval by widely varying the reader to reader distances. In thins study, a novel multi-track read channel signal processing approach that differentiates linear densities of jointly processing tracks is suggested and numerically evaluated. For an ARMR with the 3 reader 2 track setup shows around 4% of potential ADC gain over the constant linear density configuration under aggressive ITI condition, providing the doubled read throughput. Likewise, the multi-wordline signal processing schemes are investigated for NAND flash memory channel under severe ICI. Joint equalization can be modified for processing two or more wordlines' soft information together, while it requires additional read operations with a channel customized set of slicing levels. Evaluations with numerical flash channel model show that the joint processing of two wordlines provides bit error rate (BER) performance gain around 0.1 order with 6 additional read operations per wordline.

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Coding scheme for 3D vertical flash memory

Cited by 14 publications

References 24 publications

ReveNAND

ReveNAND

Reliability of 3D NAND Flash Memories

Advanced channel signal processing for multi-track or multi-wordline data storage systems

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