Combined packet and TDM circuit switching NoCs with novel connection configuration mechanism

Chen, Yong; Matúš, Emil; Fettweis, Gerhard

doi:10.1109/iscas.2017.8050829

Cited by 8 publications

(4 citation statements)

References 8 publications

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“…Many hybrid NoCs have been proposed in recent research. The connection setup of hybrid switch networks can be implemented by a packet configuration [ 31 , 32 , 33 , 34 ] or by a master-controlled dedicated network configuration [ 35 , 36 , 37 , 38 ].…”

Section: Related Workmentioning

confidence: 99%

“…In [ 34 ], a TDM (time division multiplexing) circuit-switched part for transferring Guaranteed Service (GS) packets and a packet-switched part for transferring best effort (BE) packets were proposed. The packet switched network utilizes the unreserved resources to increase resource utilization.…”

Section: Related Workmentioning

confidence: 99%

“…Using an 8 × 8 mesh NOC architecture and an injection rate of 0.15, we compared it with two typical packet-switched NOC networks, AEthereal [ 26 ], dAElite [ 25 ], and a hybrid NoC network CTN [ 34 ] with configuration time. It can be seen from Table 3 that the system configuration speed of our method is 125 times faster than AEtheral, 10 times faster than dAElite, and 3.8 times faster than CTN.…”

Section: Implementation and Evaluationmentioning

confidence: 99%

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PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs

2023

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Hundreds of processor cores or modules are integrated into a single chip. The traditional bus or crossbar is challenged by bandwidth, scalability, and silicon area, and cannot meet the requirements of high end applications. Network-on-chip (NoC) has become a very promising interconnection structure because of its good scalability, predictable interconnect length and delay, high bandwidth, and reusability. However, the most available packet routing NoC may not be the perfect solution for high-end heterogeneous multi-core real-time systems-on-chip (SoC) because of the excessive latency and cache cost overhead. Moreover, circuit switching is limited by the scale, connectivity flexibility, and excessive overhead of fully connected systems. To solve the above problems and to meet the need for low latency, high throughput, and flexibility, this paper proposes PCCNoC (Packet Connected Circuit NoC), a low-latency and low-overhead NoC based on both packet switching (setting-up circuit) and circuit switching (data transmission on circuit), which offers flexible routing and zero overhead of data transmission latency, making it suitable for high-end heterogeneous multi-core real-time SoC at various system scales. Compared with typically available packet switched NoC, our PCCoC sees 242% improved performance and 97% latency reduction while keeping the silicon cost relatively low.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Implementation and Evaluationmentioning

confidence: 99%

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PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs

2023

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“…The work in [6] combined a circuit-switching subnetwork that integrated TDM and SDM [20] as well as a packet switching sub-network. The work in [21] focused on the online connection configuration for a hybrid NoC, which reduces the hardware cost while still guaranteeing configuration latency.…”

Section: Hybrid Networkmentioning

confidence: 99%

The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System

Shimizu

Ito

Iizuka

et al. 2022

IEICE Trans. Inf. & Syst.

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The multi-FPGA system known as, the Flow-in-Cloud (FiC) system, is composed of mid-range FPGAs that are directly interconnected by high-speed serial links. FiC is currently being developed as a server for multi-access edge computing (MEC), which is one of the core technologies of 5G. Because the applications of MEC are sometimes timing-critical, a static time division multiplexing (STDM) network has been used on FiC. However, the STDM network exhibits the disadvantage of decreasing link utilization, especially under light traffic. To solve this problem, we propose a hybrid router that combines packet switching for low-priority communication and STDM for high-priority communication. In our hybrid network, the packet switching uses slots that are unused by the STDM; therefore, best-effort communication by packet switching and QoS guarantee communication by the STDM can be used simultaneously. Furthermore, to improve each link utilization under a low network traffic load, we propose a dynamic communication switching algorithm. In our algorithm, each router monitors the network load metrics, and according to the metrics, timing-critical tasks select the STDM according to the metrics only when congestion occurs. This can achieve both QoS guarantee and efficient utilization of each link with a small resource overhead. In our evaluation, the dynamic algorithm was up to 24.6% faster on the execution time with a high network load compared to the packet switching on a real multi-FPGA system with 24 boards.

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A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC

Koenen

Doan

Wild

et al. 2019

Architecture of Computing Systems – ARCS 2019

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Combined packet and TDM circuit switching NoCs with novel connection configuration mechanism

Cited by 8 publications

References 8 publications

PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs

PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs

The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System

A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC

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