Compact Hardware of Running Gaussian Average Algorithm for Moving Object Detection Realized on FPGA and ASIC

Abstract

Real-time detection of moving object is essential to traffic monitoring, video surveillance and many other vital applications. The effectiveness of real-time detection hinges on background subtraction. This paper proposes a hardware-efficient architecture for the running Gaussian average (RGA) technique of background subtraction. The architecture was designed based on the field programmable gate array (FPGA) and application specific integrated circuit (ASIC). The FPGA was realized using Digilent ZedBoard, while the ASIC was implemented using Cadence Genus, Innovus, and Assura tools at 45 nm process technology. A prototype of our architecture was tested with a video containing multiple moving objects, and another containing a single moving object. The results show that the proposed architecture is efficient in terms of area, power and timing. Therefore, this paper provides a background subtraction approach that uses hardware resources effectively without sacrificing the detection accuracy.