Comparative analysis of gate-oxide engineering in charge plasma based nanowire transistor

Abstract

In this work, a Hetero-Gate-Oxide Charge Plasma-based Nanowire Transistor (HGO-CPNWT) has been proposed, characterized, and a comparative analysis with the Conventional Charge Plasma-based Nanowire Transistor (CCPNWT) and the Stack-Gate-Oxide CPNWT (SGO-CPNWT) has been investigated. The effects of stacking a high-κ gate oxide with a low-κ gate oxide beneath the gate and segmenting the gate oxide with a high-κ oxide at the source side and low-κ oxide at the drain side have been analyzed with the short channel effects (SCEs) parameters and radio-frequency (RF) / analog figure of merits have been analyzed. The HGO-CPNWT demonstrates enhanced performances in terms of Ion/Ioff of 1.66×108, subthreshold slope (SS) of 65.74 mV/decade, drain induced barrier lowering (DIBL) of 47.857 mV/V, peak transconductance (gm) of 3.43×10-5 S/μm, and peak cut-off frequency (ft) of 114 GHz. The simulation employs a comprehensive quantum transport model (NEGF), and the comparative impacts of adjusting channel length (Lg), nanowire radius (r), and gate oxide thickness (Tox) are studied.