Comparative analysis of sense amplifiers for memories

Abstract

Sense amplifiers play an important role in memories like Dynamic Random Access (DRAM) and Static Random Access (SRAM) for read operations. Sense amplifier is one of the peripheral circuits in memories that are placed in each column of the memory array. A sense amplifier compares the bit line voltage and its complement, and then amplifies it to rail to rail output voltages. In this project, several latch type sense amplifier have been designed and simulated using 90nm CMOS technology with a supply voltage of 1.2V. Sensing delay is one of the important factors in sense amplifier design and it will be calculated for all sense amplifiers by performing voltage scaling.

Using Power Reduction Techniques, a Comparison of Differential and Latch Type Sense Amplifier Circuits

“…A common occurrence is an increase in the amount of parasite space used by the bit line concurrently with the expansion of the total memory capacity of the system. This bit line has been expanding [17][18][19][20] as the use of memory that requires a lot of energy has gotten increasingly widespread.…”

Comparative Analysis in Terms of Power and Delay of the Different Sense Amplifier Topologies

“…Bit lines are connected to inputs of current sense amplifiers and discharging of bit lines causes decreases in current which helps in determining the output voltage level (Abu-Rahma et al, 2011). Current sense amplifiers are widely used to reduce power and sensing delay as it amplifies the small differential signal from Bit lines and Data line Bar (DLB) quickly (Hemaprabha & Vivek, 2015;Kumar et al, 2011;Rabaey, Chandrakasan, & Nikolić, 2003) . Bit lines connected to inputs of current sense amplifiers cause' extremely high input impedance at the input, leads decoupling of Bit lines from output (Dutta & Mondal, 2020;Sinangil & Chandrakasan, 2014;Toli{\'c}, 2019;Weste & Harris, 2015) .…”