Comparator noise extraction and compensation technique for accuracy enhancement in 16 bit SAR ADC

Abstract

This paper presents a comparator noise extraction and compensation technique for accuracy enhancement utilized in 16-bit 1 MS/s fully-differential Successive-Approximation-Register Analog-to-Digital Converter (SAR ADC). Usually, 14.0-bit ENOB is easily achieved through capacitor mismatch and harmonic calibration. To decrease the noise further, comparator noise extraction technique which statistically estimates the comparator residue voltage is presented. All the measurement and correction process are on chip and in foreground. This technique is verified in a 0.18-μm 5 V CMOS process, and it measures a 2.6 dB SNR improvement and finally a 94.6 dB SNR is achieved with 1 MS/s sample clock and a 10 kHz input tone.