Comparison and analysis of various PFD architecture for a phase locked loop design

Anushkannan, N. K.; Mangalam, H.; Dharani, V. Anoor; Divya, G; Esack, N.; Gokulraj, M.

doi:10.1109/iccic.2013.6724238

Cited by 3 publications

(1 citation statement)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Various PFD architectures for PLLs are analyzed and compared in Ref. [3]. Simulations are carried out to show the performance of the different PFDs.…”

Section: Introductionmentioning

confidence: 99%

Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop

Liu¹,

Wang²,

Li³

et al. 2014

J. Semicond.

View full text Add to dashboard Cite

Two essential blocks for the PLLs based on CP, a phase-frequency detector (PFD) and an improved current steering charge-pump (CP), are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from −354° to 354° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage, swinging from 0.2 to 1.1 V, and the power consumption is 1.3 mW under a 1.2-V supply.

show abstract

“…Various PFD architectures for PLLs are analyzed and compared in Ref. [3]. Simulations are carried out to show the performance of the different PFDs.…”

Section: Introductionmentioning

confidence: 99%

Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop

Liu¹,

Wang²,

Li³

et al. 2014

J. Semicond.

View full text Add to dashboard Cite

show abstract

Design of a CMOS PFD-CP module for a PLL

Anushkannan¹,

Mangalam²

2015

Sadhana

View full text Add to dashboard Cite

This paper introduces a modified design of Phase frequency detector (PFD) with reduced dead zone and improved charge pump (CP) with reduced current mismatch for a Phase Locked Loop (PLL). Three modified PFD circuits are proposed, designed, simulated, and the results are analyzed considering dead zone as a constraint. Design of pass transistor logic network plays a part in the diminution of the dead zone. Further, an improved design of CP is proposed to reduce current mismatch. It is achieved by placing the single ended differential amplifier in currentvoltage feedback configuration which offers high output impedance. Simulations are performed using T-SPICE, implemented in IBM 0.13 µm technology under 1.3 V power supply. Results show that the modified PFD design has a dead zone of 0.3 ns and the current mismatch decrements to 0.1 µA in an improved CP design.

show abstract

Design, Analysis and Comparison of PFD Architectures for Fast Locking Frequency Synthesizer

Sharma

Johar

et al. 2019

2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)

View full text Add to dashboard Cite

Comparison and analysis of various PFD architecture for a phase locked loop design

Cited by 3 publications

References 3 publications

Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop

Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop

Design of a CMOS PFD-CP module for a PLL

Design, Analysis and Comparison of PFD Architectures for Fast Locking Frequency Synthesizer

Contact Info

Product

Resources

About