Comparison of Plasma Doping with Implant for High Performance SOI CMOS Fabrication

Abstract

New approaches have been developed to match plasma doping with ion implant for ultrashallow junction formation.This newly matched plasma doped extension junctions have been successfully implemented with other advanced device process elements such as SMT, e-SiGe and dual stress liners to achieve highest performance SOI CMOS devices yet reported with plasma doping ; PFETs and NFETs Ion at Ioff of 100 nA/ m are ~ 800 and ~ 1000 A/ m (Vdd = 1V) respectively. DIBL and subthreshold slope are 2 00 mV amd 100 mV/decade. Junction diode and large area, thin gate dielectric capacitor leakages are comparable to corresponding high performance CMOS with I/I extension. High performance RO with I/I NFETs and plasma doped PFETs achieving a stage delay of 9.9 ps (IDDQ=80 nA/st/µm) with a fanout of 3 have also been demonstrated.