Compensated Current Mirror Neuron Circuits for Linear Charge Integration with Ultralow Static Power in Spiking Neural Networks

Abstract

For energy‐ and time‐efficient artificial intelligence (AI) computing, implementing hardware‐based spiking neural networks (SNNs) has become a core technology. In SNNs, synaptic devices store weights in memory, and neurons process received weighted information and generate spike signals. Upon feeding spike signals into synaptic arrays, the synaptic weights multiply the signals, which subsequently sum up to perform vector‐matrix multiplication (VMM). Simultaneous access to multiple synaptic devices, however, reduces the equivalent resistance of these synaptic arrays. This reduction alters the voltage division between the pre‐synaptic array and the input resistance of the neuron circuit, distorting the read voltage across synaptic devices. This phenomenon is known as the fan‐in problem, which leads to non‐ideal VMM operations and degrades system accuracy. To address this issue, a novel compensated current mirror (CCM) neuron circuit is proposed, which incorporates a single additional transistor into a conventional current mirror. This CCM neuron achieves exceptional current linearity (R2 > 0.999) and efficiently compensates for VMM error with low complexity and energy consumption (3.33 pJ spike−1). Furthermore, the CCM neuron demonstrates ≈7‐%p higher inference accuracy than conventional ones when integrated with a 512 × 512 large‐scale synaptic array, which is comparable to the accuracy of software‐based SNNs.