Compilation of standard-cell libraries

Martínez, Antonio Manuel López; Dholakia, S.; Bush, Shane S.

doi:10.1109/jssc.1987.1052701

Cited by 8 publications

(7 citation statements)

References 5 publications

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“…The section also investigates the conventional design techniques for standard cells and compares that process with a newer approach, with the goal of creating cells in a quick and efficient manner. Given the lack of a standard cell compiler [8], the more rapid approach that will be introduced was not feasible for this project but serves as a potential area for future research and projects. and as a result, shorten time to market of products and systems that utilize this design method.…”

Section: -Standard Cell Library Overviewmentioning

confidence: 99%

“…The standard cells designed for this thesis utilize each of these mentioned geometric rules during layout design to fulfill the requirements for valid standard cell layouts. Next, the compiler performs full behavioral simulation for each standard cell and the complete timing and performance metrics are generated automatically [8]. Cadence tools can achieve similar operation through script usage that performs the discrete steps necessary to simulate and output performance data.…”

Section: -Traditional Standard Cell Creation Processmentioning

confidence: 99%

“…As mentioned previously, the simulations are performed under worst case conditions and Martinez et al linearized the delay outputs and placed them into a high level parameter that could be used by a model compiler. The worst case power dissipation as a function of frequency was computed for each standard cell with a software program [8].…”

Section: -Traditional Standard Cell Creation Processmentioning

confidence: 99%

“…With this data, [8] [8]. Figure 3.4 shows an example of a data sheet created by [8] for their standard cells using this approach.…”

Section: -Traditional Standard Cell Creation Processmentioning

confidence: 99%

“…The automation also creates a uniform formatting that should present itself the same way regardless of the standard cell utilized. This means that regardless of which cell is selected from the library, the corresponding data between cells will be detailed in the same document location and should make properties easy to find when working within a single library [8]. Such documentation is not within the scope of this thesis but is important to keep in mind, especially when automated techniques can generated these forms during standard cell compilation.…”

Section: Figure 34: Automatically Created Data Sheet For D Flip Flopmentioning

confidence: 99%

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Mos Current Mode Logic (Mcml) Analysis for Quiet Digital Circuitry and Creation of a Standard Cell Library for Reducing the Development Time of Mixed-Signal Chips

Marusiak¹

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Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative to CMOS in the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with the transitions. Creating a noiseless standard cell library with MCML allows use of circuitry that uses low voltage switching with 1.5V between logic levels in a quiet or mixed-signal environment as opposed to the full rail to rail swinging of CMOS logic. This allows cohesive implementation with analog circuitry on the same chip due to constant current and lower switching ranges not creating rail noise during digital switching. Standard cells allow for the Cadence tools to automatically generate circuits and Cadence serves as the development platform for the MCML standard cells. The theory surrounding MCML is examined along with current and future applications well-suited for MCML are researched and explored with the goal of highlighting valid candidate circuits for MCML. Inverters and NAND gates with varying current drives are developed to meet these specialized goals and are simulated to prove v viability for quiet, mixed-signal applications. Analysis and results show that MCML is a superior implementation choice compared to CMOS for high speed and mixed signal applications due to frequency independent power dissipation and lack of generated noise during operation. Noise results show rail current deviations of 50nA to 300nA during switching over an average operating current of 20µA to 80µA respectively. The multiple order of magnitude difference between noise and signal allow the MCML cells to dissipate constant power and thus perform with no noise added to a system. Additional simulated results of a 31-stage ring oscillator result in a frequency for MCML of 1.57GHz simulated versus the 150.35MHz that MOSIS tested on a fabricated 31-stage CMOS oscillator. The layouts designed for the standard cell library conform to existing On Semiconductor ami06 technology dimensions and allow for design of any logical function to be fabricated. The I/O signals of each cell operate at the same input and output voltage swings which allow seamless integration with each other for implementation in any logical configuration.

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Section: -Standard Cell Library Overviewmentioning

confidence: 99%

Section: -Traditional Standard Cell Creation Processmentioning

confidence: 99%

Section: -Traditional Standard Cell Creation Processmentioning

confidence: 99%

“…With this data, [8] [8]. Figure 3.4 shows an example of a data sheet created by [8] for their standard cells using this approach.…”

Section: -Traditional Standard Cell Creation Processmentioning

confidence: 99%

Section: Figure 34: Automatically Created Data Sheet For D Flip Flopmentioning

confidence: 99%