Compiler Control Power Saving Scheme for Multi Core Processors

Shirako, Jun; Oshiyama, Naoto; Wada, Yasutaka; Shikano, Hiroaki; Kimura, Keiji; Kasahara, Hironori

doi:10.1007/978-3-540-69330-7_25

Cited by 19 publications

(9 citation statements)

References 10 publications

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“…The lower the processor's voltage is used, the less the energy is consumed. The method proposed in [15][16] extends DVS from single-core [17] to multi-core processors by exploring extra potentials for the energy saving with the characteristics of the multi-core architecture.…”

Section: Related Workmentioning

confidence: 99%

Energy Efficiency of a Multi-Core Processor by Tag Reduction

Zheng

Dong

Ota

et al. 2011

J. Comput. Sci. Technol.

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We consider the energy saving problem for caches on a multi-core processor. In the previous research on low power processors, there are various methods to reduce power dissipation. Tag reduction is one of them. This paper extends the tag reduction technique on a single-core processor to a multi-core processor and investigates the potential of energy saving for multi-core processors. We formulate our approach as an equivalent problem which is to find an assignment of the whole instruction pages in the physical memory to a set of cores such that the tag-reduction conflicts for each core can be mostly avoided or reduced. We then propose three algorithms using different heuristics for this assignment problem. We provide convincing experimental results by collecting experimental data from a real operating system instead of the traditional way using a processor simulator that cannot simulate operating system functions and the full memory hierarchy. Experimental results show that our proposed algorithms can save total energy up to 83.93% on an 8-core processor and 76.16% on a 4-core processor in average compared to the one that the tag-reduction is not used for. They also significantly outperform the tag reduction based algorithm on a single-core processor.

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Section: Related Workmentioning

confidence: 99%

Energy Efficiency of a Multi-Core Processor by Tag Reduction

Zheng

Dong

Ota

et al. 2011

J. Comput. Sci. Technol.

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“…For example, Jun shirako et al [32] proposed a static compiler control scheme to reduce the power consumption of a multi-core processor without profiling. It involves a voltage/frequency control for processors and a power supply cut-off function for unnecessary processors.…”

Section: Related Workmentioning

confidence: 99%

A Power-Saving Technique for the OSGi Platform

Chen

Lin

Yan

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYWith more digital home appliances and network devices having OSGi as the software management platform, the power-saving capability of the OSGi platform has become a critical issue. This paper is aimed at improving the power-efficiency of the OSGi platform, i.e. reducing the energy consumption with minimum performance degradation. The key to this study is an efficient power-saving technique which exploits the runtime information already available in a Java virtual machine (JVM), the base software of the OSGi platform, to best determine the timing of performing DVFS (Dynamic Voltage and Frequency Scaling). This, technically, involves a phase detection scheme that identifies the memory phase of the OSGi-enabled device/server in a correct and almost effortless way. The overhead of the power-saving procedure is thus minimized, and the system performance is well maintained. We have implemented and evaluated the proposed power-saving approach on an OSGi server, where the Apache Felix OSGi implementation and the DaCapo benchmarks were applied. The results show that this approach can achieve real power-efficiency for the OSGi platform, in which the power consumption is significantly reduced and the performance remains highly competitive, compared with the other power-saving techniques.

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“…The main principle of DVFS is to suitably lower the operating voltage/frequency to exponentially reduce the energy consumption at the cost of linear performance degradation [5]. Shirako et al [10] proposed a DVFS-based energy minimization approach using a modified OpenMP compiler, named OSCAR. The compiler analyses the criticality of various parallel tasks and sections and identifies suitable DVFS for them.…”

Section: Introductionmentioning

confidence: 99%

Adaptive Energy Minimization of OpenMP Parallel Applications on Many-Core Systems

Shafik

Das

Yang

et al. 2015

Proceedings of the 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures

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Abstract-Energy minimization of parallel applications is an emerging challenge for current and future generations of manycore computing systems. In this paper, we propose a novel and scalable energy minimization approach that suitably applies DVFS in the sequential part and jointly considers DVFS and dynamic core allocations in the parallel part. Fundamental to this approach is an iterative learning based control algorithm that adapt the voltage/frequency scaling and core allocations dynamically based on workload predictions and is guided by the CPU performance counters at regular intervals. The adaptation is facilitated through performance annotations in the application codes, defined in a modified OpenMP runtime library. The proposed approach is validated on an Intel Xeon E5-2630 platform with up to 24 CPUs running NAS parallel benchmark applications. We show that our proposed approach can effectively adapt to different architecture and core allocations and minimize energy consumption by up to 17% compared to the existing approaches for a given performance requirement.Keywords-Many-core, OpenMP, Energy minimization.I. INTRODUCTION Silicon technology scaling has enabled the fabrication of many interconnected cores on a single chip for current and future generations of computing systems. The emergence of such systems has facilitated computing performance at unprecedented levels with application parallelization and architectural support. However, higher device-level integration and operating frequency in these systems have rendered exponentially increased power density and energy consumption [1]. Hence, minimizing the energy consumption, while delivering the required performance is a key design challenge for many-core applications [2], [5].The continuing performance growth of many-core applications has been facilitated by parallel programming models. OpenMP is one such programming model, considered as the de facto standard of shared memory multiprocessing [3]. It features compiler-enabled annotations that can achieve data-or task-level parallelization. The parallelization is facilitated by runtime libraries that can allocate the number of computing nodes and suitably schedule the parallel tasks and threads during runtime to achieve high performance [9].Over the years, there has been growing interest in OpenMP-based dynamic adaptation between energy and performance trade-offs of parallel applications [4]. Dynamic voltage/frequency scaling (DVFS) is a major runtime control knob to achieve such adaptation. The main principle of DVFS is to suitably lower the operating voltage/frequency to exponentially reduce the energy consumption at the cost of linear performance degradation [5]. Shirako et al.[10] proposed a DVFS-based energy minimization approach using a modified OpenMP compiler, named OSCAR. The compiler analyses the criticality of various parallel tasks and sections and identifies suitable DVFS for them. Cochran et al. [11] proposed another adaptive DVFS approach to control the peak power budget of an applicati...

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Compiler Control Power Saving Scheme for Multi Core Processors

Cited by 19 publications

References 10 publications

Energy Efficiency of a Multi-Core Processor by Tag Reduction

Energy Efficiency of a Multi-Core Processor by Tag Reduction

A Power-Saving Technique for the OSGi Platform

Adaptive Energy Minimization of OpenMP Parallel Applications on Many-Core Systems

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