Comprehensive Survey on Wireless Network on Chips

Shruthi, R.; Shashidhara, H. R.; Deepthi, M. S.

doi:10.1007/978-981-16-5747-4_18

Cited by 11 publications

(2 citation statements)

References 46 publications

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“…Hardware operating at THz band can also leverage IS to enable the transference of data on a chip-scale architecture with low latency and small power absorption for wireless networks on chips (WiNoCs) [ 145 ]. WiNoCs are used as communication backbones for integration in multi-core system-on-chip (SoC), which are appointed to provide an integrated solution to challenging design problems in the telecommunications, multimedia, and consumer electronic domains [ 146 , 147 ].…”

Section: Discussion and Research Directionsmentioning

confidence: 99%

A Survey on the Impact of Intelligent Surfaces in the Terahertz Communication Channel Models

E Silva,

Ribeiro,

Adanvo

et al. 2023

Sensors

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Terahertz (THz) band will play an important role in enabling sixth generation (6G) envisioned applications. Compared with lower frequency signals, THz waves are severely attenuated by the atmosphere temperature, pressure, and humidity. Thus, designing a THz communication system must take into account how to circumvent or diminish those issues to achieve a sufficient quality of service. Different solutions are being analyzed: intelligent communication environments, ubiquitous artificial intelligence, extensive network automation, and dynamic spectrum access, among others. This survey focuses on the benefits of integrating intelligent surfaces (ISs) and THz communication systems by providing an overview of IS in wireless communications with the scanning of the recent developments, a description of the architecture, and an explanation of the operation. The survey also covers THz channel models, differentiating them based on deterministic and statistical channel modeling. The IS-aided THz channels are elucidated at the end of the survey. Finally, discussions and research directions are given to help enrich the IS field of research and guide the reader through open issues.

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Section: Discussion and Research Directionsmentioning

confidence: 99%

A Survey on the Impact of Intelligent Surfaces in the Terahertz Communication Channel Models

E Silva,

Ribeiro,

Adanvo

et al. 2023

Sensors

View full text Add to dashboard Cite

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“…The classic System-on-Chip (SoC) communication architecture based on the shared bus mechanism has faced several difficulties in recent years when hundreds or thousands of IP cores are combined on a single chip, primarily in the SoC's scalability [1]. The problem has become prominent, and the problem of limited area resources has increasingly become the bottleneck of expanding the system.…”

Section: Introductionmentioning

confidence: 99%

Design and Performance Analysis of Low Latency Routing Algorithm based NoC for MPSoC

Nagalaxmi¹,

Rao²,

Chandrasekhar³

2023

Int. j. commun. netw. inf. secur.

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The Network on Chip is appropriate where System-on-Chip technology is scalable and adaptable. The Network on Chip is a new communication architecture with a number of benefits, including scalability, flexibility, and reusability, for applications built on Multiprocessor System on a Chip (MPSoC). However, the design of efficient NoC fabric with high performance is critically complex because of its architectural parameters. Identifying a suitable scheduling algorithm to resolve arbitration among ports to obtain high-speed data transfer in the router is one of the most significant phases while designing a Network on chip based Multiprocessor System on a Chip. Low latency, throughput, space utilization, energy consumption, and reliability for Network on chip fabric are all determined by the router. The performance of the NoC system is hampered by the deadlock issues that plague conventional routing algorithms. This work develops a novel routing algorithm to address the deadlock problem. In this paper, a deterministic shortest path deadlock-free routing method is developed based on the analysis of the Turn Model. In the 2D-mesh structure, the algorithm uses separate routing methods for the odd and even columns. This minimizes the number of paths for a single channel, congestion, and latency. Two test scenarios—one with and one without a load test—were used to evaluate the proposed model. For a zero-load network, three clock cycles are utilized to transfer the packets. For the load network, five clocks are utilized to transfer the packets. The latency is measured for both cases without load and with load test and the corresponding latency is 3ns and 7ns respectively.The proposed method has an 18.57Mbps throughput. The area and power utilization for the proposed method are 69% (IO utilization) and 0.128W respectively. In order to validate the proposed method, the latency is compared with existing work and 50% latency is reduced both with and without congestion load.

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A Survey on Heterogeneous CPU–GPU Architectures and Simulators

Alaei,

Yazdanpanah

2024

Concurrency and Computation

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Heterogeneous architectures are vastly used in various high performance computing systems from IoT‐based embedded architectures to edge and cloud systems. Although heterogeneous architectures with cooperation of CPUs and GPUs and unified address space are increasingly used, there are still a lot of open questions and challenges regarding the design of these architectures. For evaluation, validation and exploration of next generation of heterogeneous CPU–GPU architectures, it is essential to use unified heterogeneous simulators for analyzing the execution of CPU–GPU workloads. This article presents a systematic review on challenges of heterogeneous CPU–GPU architectures with covering a diverse set of literatures on each challenge. The main considered challenges are shared resource management, network interconnections, task scheduling, energy consumption, and programming model. In addition, in this article, the state‐of‐the‐art of heterogeneous CPU–GPU simulation platforms is reviewed. The structure and characteristics of five cycle‐accurate heterogeneous CPU–GPU simulators are described and compared. We perform comprehensive discussions on the methodologies and challenges of designing high performance heterogeneous architectures. Moreover, for developing efficient heterogeneous CPU–GPU simulators, some recommendations are presented.

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Comprehensive Survey on Wireless Network on Chips

Cited by 11 publications

References 46 publications

A Survey on the Impact of Intelligent Surfaces in the Terahertz Communication Channel Models

A Survey on the Impact of Intelligent Surfaces in the Terahertz Communication Channel Models

Design and Performance Analysis of Low Latency Routing Algorithm based NoC for MPSoC

A Survey on Heterogeneous CPU–GPU Architectures and Simulators

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