Configurable baseband digital transceiver for Gbps wireless 60 GHz communications

Diamantopoulos, Dionysios; Galiatsatos, P.; Karachalios, Athanasios; Lentaris, George; Reisis, D.; Soudris, Dimitrios

doi:10.1109/icecs.2011.6122246

Cited by 3 publications

(1 citation statement)

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“…However, the previous standards are normally defined to support various applications and thus they include several complicated processing steps to ensure the data integrity for different transmitting scenarios. If the recent WiGig standard were applied [6,8], for example, the received data stream would be recovered by passing through a number of blocks including synchronization unit, channel estimator, de-mapper, de-interleaver, and iterative LDPC decoder [18,19]. Therefore, the previous baseband system basically suffers from the long processing latency.…”

Section: Baseband Processing With Block-level Interleaved-bch Codesmentioning

confidence: 99%

High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

et al. 2019

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This paper presents a novel baseband architecture that supports high-speed wireless VR solutions using 60 GHz RF circuits. Based on the experimental observations by our previous 60 GHz transceiver circuits, the efficient baseband architecture is proposed to enhance the quality of transmission. To achieve a zero-latency transmission, we define an (106,920, 95,040) interleaved-BCH error-correction code (ECC), which removes iterative processing steps in the previous LDPC ECC standardized for the near-field wireless communication. Introducing the block-level interleaving, the proposed baseband processing successfully scatters the existing burst errors to the small-sized component codes, and recovers up to 1080 consecutive bit errors in a data frame of 106,920 bits. To support the high-speed wireless VR system, we also design the massive-parallel BCH encoder and decoder, which is tightly connected to the block-level interleaver and de-interleaver. Including the high-speed analog interfaces for the external devices, the proposed baseband architecture is designed in 65 nm CMOS, supporting a data rate of up to 12.8 Gbps. Experimental results show that the proposed wireless VR solution can transfer up to 4 K high-resolution video streams without using time-consuming compression and decompression, successfully achieving a transfer latency of 1 ms.

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Section: Baseband Processing With Block-level Interleaved-bch Codesmentioning

confidence: 99%