Configurable Logic Gates Using Polarity-Controlled Silicon Nanowire Gate-All-Around FETs

Marchi, Michele De; Zhang, Jian; Frache, Stefano; Sacchetto, Davide; Gaillardon, Pierre-Emmanuel; Leblebici, Yusuf; Micheli, Giovanni De

doi:10.1109/led.2014.2329919

Cited by 106 publications

(55 citation statements)

References 7 publications

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“…Instead of the conventional selective doping process, reconfigurable FET technologies can change polarity (n-or p-type) during operation by setting a polarity gate electrode (PG) bias [3,4,5,6]. The type of charge carrier for the conduction is determined by the appropriate gate voltage tuning at the Schottky junction of the source region.…”

Section: Reconfigurable Operationmentioning

confidence: 99%

“…Unlike to the conventional complementary metal-oxide-semiconductor (CMOS) devices which have static electrical functions determined during the fabrication, reconfigurable FETs (RFETs) are dynamically programmable to n-or p-type FET by changing electric signals during the operation. Thus, it is desirable for the highly adaptable logic architectures with their enhanced functionality [3,4,5,6]. Reducing the power consumption is another technical issue for future logic device technology.…”

Section: Introductionmentioning

confidence: 99%

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Reconfigurable U-shaped tunnel field-effect transistor

Lee

kwon

Choi

et al. 2017

IEICE Electron. Express

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A reconfigurable U-shaped tunnel field-effect transistor (RUT-FET) is proposed as a low-power dynamically programmable logic device. It has several advantages over conventional reconfigurable TFETs: 1) Excellent scalability without any degradation of subthreshold swing (SS) and draininduced barrier thinning (DIBT) with recessed channel structure. 2) High current drivability with increased band-to-band tunneling junction 3) Scaling of SS with tunneling barrier width defined by geometrical parameters. In this manuscript, its electrical characteristics are examined by technology computer-aided design (TCAD) simulation. It shows ∼30× higher ON-state current than control devices and 41.8 mV/dec-SS during drain current increase by five orders magnitude. The reconfigurable operations for nand p-type FETs are also discussed.

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Section: Reconfigurable Operationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Reconfigurable U-shaped tunnel field-effect transistor

Lee

kwon

Choi

et al. 2017

IEICE Electron. Express

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show abstract

“…Recently significant progress has been made both in understanding and designing the appropriate transport mechanisms [97][98][99] and showing the benefit of building circuits out of the reconfigurable devices [100][101][102]. If CMOS circuits are to be constructed from such devices, it has to be considered, that the geometry cannot be adjusted according to an unbalanced current output of p-channel and nchannel devices since the same device has to be usable in both configurations.…”

Section: Electron Devices Based On Silicon Nanowiresmentioning

confidence: 99%

Silicon Nanowires: Fabrication and Applications

Mikolajick

Weber

2015

NanoScience and Technology

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Due to the high surface to volume silicon ratio and unique quasi onedimensional electronic structure, silicon nanowire based devices have properties that can outperform their traditional counterparts in many ways. To fabricate silicon nanowires, in principle there are a variety of different approaches. These can be classified into top-down and bottom-up methods. The choice of fabrication method is strongly linked to the target application. From an application point of view, electron devices based on silicon nanowires are a natural extension of the downscaling of a silicon metal insulator semiconductor transistor. However, the unique properties also allow implementing new device concepts like the junctionless transistor and new functionalities like reconfigurability on the device level. Sensor devices may benefit from the high surface to volume ratio leading to a very high sensitivity of the device. Also, solar cells and anodes in Li-ion batteries can be improved by exploiting the quasi one-dimensionality. This chapter will give a review on the state-of-the-art of silicon nanowire fabrication and their application in different types of devices.

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“…This work was supported by the "Deutsche Forschungsgemeinschaft (DFG)" in the framework of the projects "ReproNano" (MI 1247/6-1 and WE4853/1-2) and "Center for Advancing Electronics Dresden" (CfAED). Simple XOR and NAND gates have already been demonstrated on chip [6]. Moreover, RFETs deliver an increased value per building block [7]- [10], enabling the mapping of complex functions with a reduced amount of hardware, e. g. NAND and NOR function can be combined in a single 4-T logic gate.…”

Section: Circuit Design With Reconfiguralbe Fetsmentioning

confidence: 99%

Effect of independently sized gates on the delay of reconfigurable silicon nanowire transistor based circuits

Trommer

Slesazeck

Weber

et al. 2015

EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon

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Reconfigurable silicon nanowire field effect transistors (RFETs) provide both operation modes of p-type and n-type field effect transistors in a single multigate device. This unique feature provides additional degrees of freedom in terms of circuit design and device layout. Here a device-circuit co-design study of a novel 1-bit full adder with only 20 transistors is presented. The delay of the adder is analyzed using the logical effort theory and compared to standard CMOS implementation. The effect of independent gate sizing on device and circuit characteristics will be discussed. It will be shown that asymmetric gates can be exploited to reduce the critical delay of the new adder by 15 %, although the individual device performance is kept constant.

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Configurable Logic Gates Using Polarity-Controlled Silicon Nanowire Gate-All-Around FETs

Cited by 106 publications

References 7 publications

Reconfigurable U-shaped tunnel field-effect transistor

Reconfigurable U-shaped tunnel field-effect transistor

Silicon Nanowires: Fabrication and Applications

Effect of independently sized gates on the delay of reconfigurable silicon nanowire transistor based circuits

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