Configurable MIMO symbol detector for wireless communication systems

Jang, Soohyun; Cheon, Jeonghyeon; Jung, Yunho

doi:10.1109/isocc.2015.7401707

Cited by 1 publication

(2 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In order to solve these complexity problems, the vigorous research has been conducted in recent decades [14][15][16][17][18]. Among them, a modified ML (MML) detection algorithm [14], which would reduce the complexity by the ratio of 1/M, was proposed, and was applied to several implementations such as [15] and [17].…”

Section: Introductionmentioning

confidence: 99%

“…Among them, a modified ML (MML) detection algorithm [14], which would reduce the complexity by the ratio of 1/M, was proposed, and was applied to several implementations such as [15] and [17]. Since recent communication systems mostly support two transmit and two receive antennas to be incorporated into a mobile device, MML detection can be considered as suitable for the symbol detector of those systems because its complexity is proportional to only M. Moreover, MML detection does not require the complex matrix computation such as QR decomposition.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Low-Complexity and Low-Power MIMO Symbol Detector for Mobile Devices with Two TX/RX Antennas

Jang¹,

Lee²,

Jung

2015

JSTS:Journal of Semiconductor Technology and Science

Self Cite

View full text Add to dashboard Cite

Abstract-In this paper, a low-complexity and lowpower soft output multiple input multiple output (MIMO) symbol detector is proposed for mobile devices with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode in single hardware and shows the optimal maximum likelihood (ML) performance. By applying a multistage pipeline structure and using a complex multiplier based on the polar-coordinate, the complexity of the proposed architecture is dramatically decreased. Also, by applying a clockgating scheme to the internal modules for MIMO modes, the power consumption is also reduced. The proposed symbol detector was designed using a hardware description language (HDL) and implemented using a 65nm CMOS standard cell library. With the proposed architecture, the proposed MIMO detector takes up an area of approximately 0.31mm 2 with 183K equivalent gates and achieves a 150Mbps throughput. Also, the power estimation results show that the proposed MIMO detector can reduce the power consumption by a maximum of 85% for the various test cases.

show abstract