Cost-effective and low-power memory address bus encodings

Abstract

this paper presents encoding methods that build on T0-encoding to achieve considerable reduction in memory address bus wires with small performance overhead, while reducing address bus switching activity. The known T0-encoding is combined with a variable cycle transmission technique that uses the T0's increment signal (INC) as an indicator of the number of cycles. Two of the proposed methods maintain the energy efficiency that is significantly reduced due to time-multiplexing.Benchmark experiments show that wire count of the instruction memory address bus can be reduced by around half at the price of 12.89% average performance penalty, while maintaining the low switching activity of the original T0-encoded bus.