Cost-effective Resilient FPGA-based LDPC Decoder Architecture

Souza, Eduardo Nunes de; Nazar, Gabriel L.

doi:10.1109/iolts.2019.8854457

Cited by 1 publication

(2 citation statements)

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“…In addition, the configuration memory is typically larger than user memory, so SEUs on the configuration memories are a critical problem for the reliability of SRAM-FPGA implemented modules on OBP. As reported in [11] and [12], a single error on the configuration memory of a FPGA based LDPC decoder can substantially degrade the decoding performance, or even paralyze the LDPC decoder if the SEU occurs on the control logic of decoder. Therefore, the protection of LDPC Decoders on OBP against SEUs on the configuration memories of FPGA is an important issue.…”

Section: Introductionmentioning

confidence: 99%

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Efficient Protection of FPGA Implemented LDPC Decoders Against Single Event Upsets (SEUs) on Configuration Memories

Gao

Cheng

Liu

et al. 2023

IEEE Trans. Circuits Syst. I

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Low Density Parity Check (LDPC) codes are used in 5G systems for traffic channels due to their excellent error correction capability for long sequences, and the Min-Sum algorithm is widely applied in practical implementations of LDPC decoders due to its low complexity. If the decoder is implemented on a SRAM-based field-programmable gate array (SRAM-FPGA), the radiation-induced single-event upsets (SEUs) can affect the operation of the LDPC decoder by corrupting the configuration memory, which can change the circuit functionality and will not be corrected unless the FPGA is reconfigured. Therefore, protection of LDPC decoders with low overhead is an important problem, especially for resource-limited on-board space systems. In this paper, an efficient Duplicate With Comparison (DWC) protection scheme is proposed based on the different distribution of the parity check sum of the LDPC decoder in the error-free case and the faulty case. In particular, the check sum accumulation number and threshold are optimized to achieve high detection probability with short delay. FPGA based implementation and hardware fault injection experiments are conducted to evaluate the performance of the proposed schemes.Experimental results show that, the effect of SEUs on the LDPC decoder can be completely eliminated by the proposed scheme with 2x times computational overhead and 1.69x times power consumption overhead compared to the unprotected decoder.

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Section: Introductionmentioning

confidence: 99%

“…This model cannot be applied for the effect of SEUs on the configuration memory of an FPGA based implementation [10]. In summary, all these works only considered the computing components of the decoder in their protection scheme and did not consider the control and interconnection logic that are shown to be more fragile in [11].…”

Section: Introductionmentioning

confidence: 99%