Cross-layer fault-space pruning for hardware-assisted fault injection

Dietrich, Christian; Schmider, Achim; Pusz, Oskar; Vayá, Guillermo Payá; Lohmann, Daniel

doi:10.1145/3195970.3196019

Cited by 3 publications

(2 citation statements)

References 21 publications

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“…Meanwhile, fault cones have previously been studied in the context of multiple applications (e.g. [3,9,23,29,30,37,44,46]). For example, based on fault cones, [37] proposed a new method to obtain various distinct propagation paths for faults for n-detect.…”

Section: Previous Workmentioning

confidence: 99%

“…The authors of [23] graded the extent of strong fault-secureness with fault cone analysis (no fault-masking or path-sensitization if the fault cone sets are disjoint) for circuit robustness based on the detectability of faults. Similarly, also for robustness, in [3], an online fault-space pruning method for fault injection had been proposed. Analysis was performed by exploring the fault propagation to the next clock cycle state and fault masking with the circuit logic elements' fault cones.…”

Section: Previous Workmentioning

confidence: 99%

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Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift

et al. 2023

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Test sets that target standard fault models may not always be sufficient for detecting all defects. To evaluate test sets for the detection of unmodeled defects, n-detect test sets (which detect all modeled faults at least n times) have previously been proposed. Unfortunately, n-detect test sets are often prohibitively long. In this paper, we investigate the ability of shadow flip-flops connected into a MISR (Multiple Input Signature Register) to detect stuck-at faults fortuitously multiple times during scan shift. We explore which flip-flops should be shadowed to increase the value of n for the least detected stuck-at faults for each circuit studied. We then identify which circuit characteristics are most important for determining the cost of the MISR needed to achieve high values of n. For example, circuits that contain a few flip-flops with upstream fault cones that cover a large percentage of all faults in the circuit can often achieve high n-detect coverage fortuitously with a low-cost MISR. This allows a DFT engineer to predict the viability of this MISR-based approach early in the design cycle.

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