Cu-Filling Behavior in TSV with Positions in Wafer Level

Lee, Soon‐Jae; Jang, Youngjoo; Lee, Jun-Hyeong; Jung, Jae Pil

doi:10.6117/kmeps.2014.21.4.091

Cited by 7 publications

(9 citation statements)

References 12 publications

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“…Only by super-conformal formation Figure 8c where faster plating occurs from the bottom of the TSV is flawless filling is possible. Super-conformal formation of TSV has been reported by Hoffmann et al [47] and the authors [46]. [44], (b) conformal [45], and (c) super-conformal filling [46].…”

Section: Tsv Fillingmentioning

confidence: 87%

“…Super-conformal formation of TSV has been reported by Hoffmann et al [47] and the authors [46]. [44], (b) conformal [45], and (c) super-conformal filling [46].…”

Section: Tsv Fillingmentioning

confidence: 87%

“…However, during the electroplating process, electric current concentrates at the entrance corner of TSV, which is one of the reasons for flaws in the TSV. TSV can categorize into three types-sub-conformal, conformal, and superconformal-by the shape that TSV is being filled, as shown in Figure 8 [44][45][46]. During sub-conformal formation Figure 8a due to the faster plating speed at the entrance corner of TSV by higher current density, the opening is closed before the internal part of TSV is filled.…”

Section: Tsv Fillingmentioning

confidence: 99%

“…Electroplating done using pulsed currents had difficulties in getting flawless fillings in the TSV. Lee et al [46] have reported using periodic pulse reverse (PPR) when filling Cu in TSV. The authors have shown that when the reduction current is −7 to −10 mA/cm 2 , the oxidation current is 30-50 mA/cm 2 , and the distance between the anode and cathode is 3 cm, the sub-conformal shape was formed and created defects such as void and seam.…”

Section: Tsv Fillingmentioning

confidence: 99%

See 3 more Smart Citations

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Cho

Seo

Kim

et al. 2021

Metals

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With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.

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Section: Tsv Fillingmentioning

confidence: 87%

“…Super-conformal formation of TSV has been reported by Hoffmann et al [47] and the authors [46]. [44], (b) conformal [45], and (c) super-conformal filling [46].…”

Section: Tsv Fillingmentioning

confidence: 87%

Section: Tsv Fillingmentioning

confidence: 99%

Section: Tsv Fillingmentioning

confidence: 99%

See 2 more Smart Citations

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Cho

Seo

Kim

et al. 2021

Metals

View full text Add to dashboard Cite

show abstract

“…11,12) Therefore, an alternative plating process employing a plating solution which has lower additive concentration has been studied. [11][12][13][14][15][16][17] The objective of this study is to nd optimum leveler concentration to ll via without using accelerator and suppressor. In this study, accelerator and suppressor were not added to reduce the concentration of organic additives.…”

Section: Introductionmentioning

confidence: 99%

Effects of Leveler Concentration in High Aspect Ratio Via Filling in 3D SiP

et al. 2017

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Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

Jang,

Sharma,

Jung

2023

Materials

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Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for achieving high-density integration, high-speed connectivity, and for downsizing of electronic devices. This paper describes recent developments in TSV fabrication and bonding methods in advanced 3D electronic packaging. In particular, the authors have overviewed the recent progress in the fabrication of TSV, various etching and functional layers, and conductive filling of TSVs, as well as bonding materials such as low-temperature nano-modified solders, transient liquid phase (TLP) bonding, Cu pillars, composite hybrids, and bump-free bonding, as well as the role of emerging high entropy alloy (HEA) solders in 3D microelectronic packaging. This paper serves as a guideline enumerating the current developments in 3D packaging that allow Si semiconductors to deliver improved performance and power efficiency.

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Cu-Filling Behavior in TSV with Positions in Wafer Level

Cited by 7 publications

References 12 publications

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Effects of Leveler Concentration in High Aspect Ratio Via Filling in 3D SiP

Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

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