Current-Bunch: A Fast and Accurate Tool to Extract and Optimize Parasitics of Power Packaging

Wang, Liang; Zeng, Zheng; Yu, Yue; Ou, Kaihong; Wang, Jin

doi:10.1109/ecce44975.2020.9236262

Cited by 5 publications

(1 citation statement)

References 22 publications

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“…Recent developments brought FFT-accelerated partial element equivalent circuit (PEEC) [3] and volume integral equation (VIE) [4] methods, achieving a significant reduction in computation time while maintaining good accuracy. An even higher improvement has been achieved using the Current Bunch concept and loopbased method at the cost of accuracy [5]. As power module layouts are normally constrained by the fixed packaging dimensions, such as two-layer ceramic with copper traces on one side only, and can be approximately treated as 2.5D structures, makes them a good candidate for a fundamentally different approach to parasitic inductance extraction with the help of machine learning.…”

Section: Introductionmentioning

confidence: 99%

Ultra-Fast Power Module Inductance Estimation using Convolutional Neural Networks

Kubulus,

Michal Beczkowski,

Munk-Nielsen

et al. 2023

2023 IEEE Energy Conversion Congress and Exposition (ECCE)

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The widespread usage of wide bandgap (WBG) semiconductors forces extra emphasis on the early estimation of the layout parasitic elements. Be it a printed circuit board or a power module, layout optimization is necessary to minimize the negative effects of present inductances. Unfortunately, multiple invocations of inductance extraction software can be timeconsuming. In this work, state-of-the-art convolutional neural networks (CNN) are applied in order to lower the time consumption of inductance estimation without compromising the accuracy.

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Section: Introductionmentioning

confidence: 99%