Current-related sensitivity optimization of CMOS five-contact vertical Hall sensor

Lyu, Fei; Wang, Yu

doi:10.1016/j.jmmm.2019.166069

Cited by 5 publications

(3 citation statements)

References 27 publications

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“…The most straightforward and promising way to implement 3D Hall sensors is to arrange multiple HHSs and vertical Hall sensors (VHSs) to detect magnetic fields orthogonal and parallel to the surface, respectively. VHSs with low sensitivity and especially large offsets are a weakness of the implementation of 3D Hall sensors [ 13 , 14 , 15 ].…”

Section: Introductionmentioning

confidence: 99%

“…After the development of the five-contact VHS (5CVHS) in [ 16 ], several variations have been proposed to improve the performance of VHSs, such as the four-contact VHS (4CVHS) [ 17 , 18 ], six-contact VHS (6CVHS) [ 19 ], and eight-contact circular vertical Hall devices (8CCVHD) [ 20 ]. The 5CVHS is a research hotspot to improve its performance [ 13 , 14 , 15 ], and variations have been proposed to reduce the offset by a large loss of sensitivity to accommodate low-voltage CMOS technology [ 21 , 22 ]. A symmetric four-folded and three-contact VHS (4F-3CVHS) has been proposed to reduce offset [ 23 , 24 , 25 , 26 ].…”

Section: Introductionmentioning

confidence: 99%

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A New Design of a CMOS Vertical Hall Sensor with a Low Offset

Lyu

Huang

et al. 2022

Sensors

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Vertical Hall sensors (VHSs), compatible with complementary metal oxide semiconductor (CMOS) technology, are used to detect magnetic fields in the plane of the sensor. In previous studies, their performance was limited by a large offset. This paper reports on a novel CMOS seven-contact VHS (7CVHS), which is formed by adding two additional contacts to a traditional five-contact VHS (5CVHS) to alleviate the offset. The offset voltage and offset magnetic field of the 7CVHS are reduced by 90.20% and 88.31% of those of the 5CVHS, respectively, with a 16.16% current-related sensitivity loss. Moreover, the size and positions of the contacts are optimized in standard GLOBALFOUNDRIES 0.18 μm BCDliteTM technology by scanning parameters using FEM simulations. The simulation data are analyzed in groups to study the influence of the size and contact positions on the current-related sensitivity, offset voltage, and offset magnetic field.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A New Design of a CMOS Vertical Hall Sensor with a Low Offset

Lyu

Huang

et al. 2022

Sensors

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“…In recent years, various techniques have been proposed to enhance the magnetic sensitivity of VHDs. The influence of structure size and technology on the sensitivity of the fivecontact VHD was studied by Finite Element Method (FEM) simulations [18], and the modification of the process conditions is suggested to improve sensitivity. A vertical Hall plate structure with a high negative differential sensitivity is also put forward [19], applying novel signal extraction techniques for sensitivity enhancement.…”

Section: Introductionmentioning

confidence: 99%

Sensitivity Improvement of a Fully Symmetric Vertical Hall Device Fabricated in 0.18 μm Low-Voltage CMOS Technology

Huang

2021

IEEE J. Electron Devices Soc.

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This paper proposes a new implementation method to significantly improve the magnetic sensitivity of a fully symmetric vertical Hall device (FSVHD) based on low-voltage CMOS technology. The FSVHD consists of four identical threecontact vertical Hall elements (3CVHE) and each 3CVHE is located in a low-doped deep n-well. The terminals of the 3CVHE are n + implanted in an n-well and a p + implantation in a p-well is performed to act as a trench between two adjacent n + contacts, enabling Hall current flowing deeply for sensitivity improvement. The influence of the geometry sizes on magnetic sensitivity is exploited utilizing TCAD simulation to obtain the optimized device structure in a 0.18 μm CMOS standard technology. The experimental results reveal that the proposed FSVHD with a p + /pwell trench can attain an improved voltage-related sensitivity of 8.4 mV/VT, which is about 70% higher than that of a conventional FSVHD without a trench in the same CMOS fabrication process, while offset and noise are not degraded. The proposed p + /p-well implantation trench is a good solution to enhance the sensitivity of a low-voltage CMOS VHD with a low manufacturing cost.

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