Current SiC Power Device Development, Material Defect Measurements and Characterization at Bosch

Baierhofer, Daniel

doi:10.1109/essderc.2019.8901792

Cited by 3 publications

(4 citation statements)

References 17 publications

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“…The devices were manufactured following the same manufacturing process flow for Trench-MOSFETs. A general overview of this process flow for Trench-MOSFETs can be found elsewhere [8]. Lasertec's SICA88 was used for surface and crystallographic defect analysis.…”

Section: Methodsmentioning

confidence: 99%

Correlation of Extended Defects with Electrical Yield of SiC MOSFET Devices

Baierhofer

Thomas

Staiger

et al. 2023

DDF

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The quality of the silicon carbide (SiC) epitaxial layer, i.e., layer homogeneities and extended defect densities, is of highest importance for high power 4H-SiC trench metal-oxide-semiconductor field effect transistors (Trench-MOSFET) devices. Especially, yield for devices with a large chip area is severely impacted by extended defects. Previously, devices had to be fully manufactured to effectively gauge the impact of a reduction in extended defect densities in the epitaxial layers on device yield. The production of devices such as Trench-MOSFETs is an extensive procedure. Therefore, a correlation between extended defects in the epitaxial layer and electrical device failure would allow to reliably estimate the impact of process changes during epitaxial layer deposition on electrical device yield.For this reason, n-type epitaxial layers were grown on around 1,000 commercially available 150 mm 4H-SiC Si-face substrates, which received a chemical wet cleaning prior to the epitaxy deposition. Substrates with lowest micro-pipe density from two different suppliers were used. The wafers were characterized with the corresponding device layout for defects utilizing surface microscopy as well as ultraviolet photoluminescence techniques. Subsequently, these wafers were used to produce more than 500,000 Trench-MOSFET devices. All devices have been tested on wafer level for their initial electrical integrity.With these methods a precise correlation between extended defects in the epitaxial layer and electrical failures on wafer level could be found. The influence of different substrates on the defect-based yield prediction regarding the electrical yield on wafer level is discussed. Additionally, a calculated kill-ratio is presented and the severity of defect classes on initial device failure, e.g., stacking faults, and their key failures modes are discussed.

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Section: Methodsmentioning

confidence: 99%

Correlation of Extended Defects with Electrical Yield of SiC MOSFET Devices

Baierhofer

Thomas

Staiger

et al. 2023

DDF

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“…Silicon carbide (SiC), more precisely the 4H polytype, is of increasing interest as a material for high power and high voltage devices due to its wide band-gap, electrical properties as well as thermal properties [1][2][3]. These characteristics allow the fabrication of small and efficient devices, compared to established silicon technology, e.g.…”

Section: Introductionmentioning

confidence: 99%

“…This includes the quality of layer thickness, roughness, doping concentration and respective homogeneities, as well as surface and crystallographic defect densities [4][5][6]. Existing imperfections in the SiC substrate can act as nucleation centres for additional defects in the epitaxial layer [1,4,6]. Carefully chosen epitaxial growth parameters allow for the transformation into other defect types, harmless for device operation [1,4,6].…”

Section: Introductionmentioning

confidence: 99%

“…Existing imperfections in the SiC substrate can act as nucleation centres for additional defects in the epitaxial layer [1,4,6]. Carefully chosen epitaxial growth parameters allow for the transformation into other defect types, harmless for device operation [1,4,6]. Further classification in device critical defects (CDs) and non-critical defects has to be made, since not all defects present in the epitaxial layer cause device failures or device degradation, as their effect is also dependent on the device type [7].…”

Section: Introductionmentioning

confidence: 99%

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Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth

Baierhofer

Thomas

Staiger

et al. 2022

MSF

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The yield of high power 4H-SiC Trench-MOSFET devices, especially for those with large chip area, is largely dependent on the quality of the underlying epitaxial layers and therefore low densities of critical defects are of utmost importance. Different growth conditions for the deposition of epitaxial layers were investigated to reduce the impact of defects on electrical device performance. For this investigation, 12 μm thick n-type epitaxial layers were grown varying growth rates for the buffer and the drift layer in a warm-wall chemical vapor deposition reactor. The defects in the epitaxial layers were characterized utilizing surface microscopy as well as ultraviolet photoluminescence techniques. A quantitative comparison of surface defects and crystallographic defects between the different growth conditions was conducted with these methods. The impact of the growth conditions on the formation of critical defects is discussed in detail. The reduction of critical defects, which resulted in an increase of the predicted die yield, as well as an outlook on future investigations, is discussed.

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Optoelectronic and structural characterization of trapezoidal defects in 4H-SiC epilayers and the effect on MOSFET reliability

El Hageali,

Guthrey,

Johnston

et al. 2023

Journal of Applied Physics

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To this day, trapezoidal defects are found in clusters and high counts in wafers representing the industry standard in terms of material quality being produced. This study sheds light on the nature, origin, behavior, and impact of this defect on device yield and reliability. Trapezoidal defects in 4H-SiC epitaxial layers were investigated by photoluminescence (PL) imaging, scanning electron microscopy (SEM), cathodoluminescence spectrum imaging (CLSI), SEM electron beam induced current (EBIC) imaging, and by transmission electron microscopy (TEM) observation. The bar-shaped stacking faults were identified by the PL and CL measurements with a peak emission wavelength of 420 and 450 nm. An optoelectronic behavioral study based on the recombination enhanced dislocation glide mechanism revealed how expanding dislocations and stacking faults interact with each other. Combining the luminescence and microscopy results, the nature of the stacking faults was identified as being a combination of Shockley-type and Frank-type stacking faults. The TEM analysis showed that these defects originate from the substrate and the stacking sequences of some of the faults were determined as (…2, 4, 2…) and (…2, 3, 2…) in the Zhdanov's notation by high-resolution TEM. The origin of this defect is speculated based on our results and previous reports. The EBIC imaging showed that the high density of SFs in these towers is a strong site of carrier recombination, which presumably has an impact on the transfer characteristics of SiC devices. Furthermore, these defects have shown to impact metal oxide semiconductor field effect transistors electrical performance via an increase in the on-state resistance depending on the coverage percentage of the tower of defects in the active area of the device.

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Current SiC Power Device Development, Material Defect Measurements and Characterization at Bosch

Cited by 3 publications

References 17 publications

Correlation of Extended Defects with Electrical Yield of SiC MOSFET Devices

Correlation of Extended Defects with Electrical Yield of SiC MOSFET Devices

Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth

Optoelectronic and structural characterization of trapezoidal defects in 4H-SiC epilayers and the effect on MOSFET reliability

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