Cycle precise core based hardware/software system simulation with predictable event propagation

Pétrot, Frédéric; Hommais, Denis; Greiner, Alain

doi:10.1109/eurmic.1997.617257

Cited by 20 publications

(8 citation statements)

References 5 publications

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“…The Interface Module has been described in C for cycle true simulation under CASS [15] of complete systems. This allows to evaluate the performance of each template accurately.…”

Section: Resultsmentioning

confidence: 99%

A practical tool box for system level communication synthesis

Hommais

Pétrot

Augé

2001

Proceedings of the Ninth International Symposium on Hardware/Software Codesign - CODES '01

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Fr6d6ric P6trot and Ivan Aug6 #quipe ASIM/LIP6 Unlversit6 Pierre et Marie Curie Paris, France Denis. Hommais @ lip6.fr --Frederic.Petrot @ lip6.fr --Ivan.Auge @ lip6.fr A B S T R A C TThis paper presents a practical approach to communication synthesis for hardware/software system specified as tasks communicating through lossless blocking channels. It relics on a limited set of templates that characterize the way data are exchanged between tasks realized either in software or in hardware. The templates are highly portable because their software part is implemented using the POSIX thread functions, and their hardware part is a hand crafted synthesizable module with a System VCI interface.These Interface Modules allow simple Virtual Component reuse since they not only implemeat protocol compatibility through the use of the System VCI/OCB standard but also system level communications through semantics widely accepted in the design community.

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“…The Interface Module has been described in C for cycle true simulation under CASS [15] of complete systems. This allows to evaluate the performance of each template accurately.…”

Section: Resultsmentioning

confidence: 99%

A practical tool box for system level communication synthesis

Hommais

Pétrot

Augé

2001

Proceedings of the Ninth International Symposium on Hardware/Software Codesign - CODES '01

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“…It determines a static execution order between processes based on the intraprocess dependencies. Most of the approaches in the literature assume that the dependency graph is acyclic, claiming that cycles can not be written in synthesizable code [4], [21]. Unfortunately, cyclic dependencies are not as rare as one may think (projects systemcaes, a_vhd_16550_uart and plasma from [19]).…”

Section: B Static and Dynamic Schedulingmentioning

confidence: 99%

Code Manipulation for Virtual Platform Integration

Vinco

Guarnieri

Fummi

2016

IEEE Trans. Comput.

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Simulation speed is crucial in virtual platforms, in order to enhance the design flow with early validation and design space exploration. This work tackles this challenge by focusing on two main techniques for speeding up virtual platform simulation, namely efficient data types implementation and a novel scheduling technique. Both the optimizations are obtained through code manipulation. The target language is C++ and its extensions (i.e., SystemC), that are the most widespread languages for virtual platform modeling and simulation. The optimization techniques are considered orthogonal, as they target different aspects of the simulated code. Experimental results prove the effectiveness of both the single techniques and of their combined application on complex case studies, with the result of reaching a maximum speedup of 70x in the simulation of a virtual platform.

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“…Disydent (Digital System Design Environment [2]) is also based upon KPN and uses point-to-point channels. It comes with a cycle accurate bit accurate simulator [12].…”

Section: Related Workmentioning

confidence: 99%

Monitoring communication channels on a shared memory multi-processor system on chip

Genius¹,

Pouillon²

2011

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

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To meet performance requirements, streaming applications have been mapped to Multi-Processor System on Chip (MPSoC). The Kahn Process Network (KPN) paradigm is sufficient when dealing with pipeline parallelism, but such pointto-point channels are impractical in the presence of massive task farm parallelism.Multi Writer Multi Reader (MWMR) channels generalize KPN in such a way that multiple writers and multiple readers access the same channel. They are implemented as software channels stored in on-chip memory to accommodate access by hardware and software tasks alike. The price to pay for this implementation is increased traffic to and from memory.Typical representatives are telecommunication applications which may treat hundreds or thousands of flows at a time, where the same chain of treatments is applied to every packet. The latency for this treatment depends on the packet's content, and can thus not be foreseen. Among multiple tasks which access a MWMR channel, the time to obtain a lock is variable. In consequence, fill states of MWMR channels vary heavily and it is crucial to monitor it in order to detect potential bottlenecks. We show how this can be done early in the design process by using SoCLib/DSX.

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Cycle precise core based hardware/software system simulation with predictable event propagation

Cited by 20 publications

References 5 publications

A practical tool box for system level communication synthesis

A practical tool box for system level communication synthesis

Code Manipulation for Virtual Platform Integration

Monitoring communication channels on a shared memory multi-processor system on chip

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