Cyclic stress tests for full scan circuits

Dabholkar, V.; Chakravarty, S.; Najm, J.; Patel, Jigar

doi:10.1109/vtest.1995.512622

Proceedings 13th IEEE VLSI Test Symposium 1995

DOI: 10.1109/vtest.1995.512622

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Cyclic stress tests for full scan circuits

V. Dabholkar

S. Chakravarty

J. Najm

et al.

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Cited by 5 publications

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Computing stress tests for interconnect defects

Dabholkar

Chakravarty

Proceedings Sixth Asian Test Symposium (ATS'97)

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Reliability screens are used to reduce infant mortality,The quality of the stress test set used during ?he screening process has a direct bearing on the effectiveness of the screen. We have formally studied the problem of computing good quality stress tests for some commonly occurring defects like gate-oxide shorts and interconnect defects. Methods to compute stress tests for gate-oxide defects have been discussed elsewhere. Here we present a formal study of the problem of computing stress tests for interconnect defects.

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Computing stress tests for interconnect defects

Dabholkar

Chakravarty

Proceedings Sixth Asian Test Symposium (ATS'97)

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Automatic Functional Stress Pattern Generation for SoC Reliability Characterization

Appello

Bernardi

Cagliesi³

et al. 2009

2009 14th IEEE European Test Symposium

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Computing stress tests for gate-oxide shorts

Dabholkar

Chakravarty

Proceedings Eleventh International Conference on VLSI Design

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Cyclic stress tests for full scan circuits

Cited by 5 publications

References 8 publications

Computing stress tests for interconnect defects

Computing stress tests for interconnect defects

Automatic Functional Stress Pattern Generation for SoC Reliability Characterization

Computing stress tests for gate-oxide shorts

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