Decoupling capacitor calculations for CMOS circuits

Smith, Larry

doi:10.1109/epep.1994.594099

Cited by 70 publications

(35 citation statements)

References 6 publications

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“…12(e) shows the conventional model in [3], which ignores the distances and locations of the decoupling capacitors. The board parasitic is ignored in the conventional models in [3] and [4]. Fig.…”

Section: Resultsmentioning

confidence: 99%

“…9(a). The conventional models in [3] and [4] are represented as parallel-connected circuits, as illustrated in Fig. 9(b) and (c), respectively.…”

Section: B Interference Of Current Paths Between Decoupling Capacitorsmentioning

confidence: 99%

“…8. The conventional model in [3] does not consider the distance between view port and the decoupling capacitors. As shown in Fig.…”

Section: B Interference Of Current Paths Between Decoupling Capacitorsmentioning

confidence: 99%

“…In the PEEC model, the number of unit cells was 1200, and the simulation time on a workstation was 2 h 40 min. On the contrary, in the lumped circuit model, the number of the circuit elements was about 30 [3], [4], and the simulation time on the same workstation was 5 min. In many cases, the lumped circuit models are simple enough to be calculated by pencils.…”

Section: Introductionmentioning

confidence: 99%

“…Based on the lumped circuit models, extensive research [3], [4] had been carried out to determine the locations and values of the decoupling capacitors. Unfortunately, they usually failed to design reliable power distribution network for practical applications, since the designed power-bus shows some errors on impedance over a wide range of frequencies.…”

Section: Introductionmentioning

confidence: 99%

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An efficient path-based equivalent circuit model for design, synthesis, and optimization of power distribution networks in multilayer printed circuit boards

Kim

Yoon

Lee

et al. 2004

IEEE Trans. Adv. Packag.

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Abstract-In high-speed printed circuit boards, the decoupling capacitors are commonly used to mitigate the power-bus noise that causes many signal integrity problems. It is very important to determine their proper locations and values so that the power distribution network should have low impedance over a wide range of frequencies, which demands a precise power-bus model considering the decoupling capacitors. However, conventional power-bus models suffer from various problems, i.e., the numerical analyzes require huge computation while the lumped circuit models show poor accuracy. In this paper, a novel power-bus model has been proposed, which simplifies the n-port Z-parameters of a power-bus plane to a lumped T-network circuit model. It exploits the pathbased equivalent circuit model to consider the interference of the current paths between the decoupling capacitors, while the conventional lumped models assume that all decoupling capacitors are connected in parallel, independently with each other. It also models the equivalent electrical parameters of the board parasitic precisely, while the conventional lumped models employ only the inter-plane capacitance of the power-ground planes. Although it is a lumped model for fast and easy calculation, experimental results show that the proposed model is almost as precise as the numerical analysis. Consequently, the proposed model enables a quick and accurate optimization of power distribution networks in the frequency domain by determining the locations and values of the decoupling capacitors.Index Terms-Decoupling capacitors, equivalent circuit model, power-bus distribution network.

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Section: Resultsmentioning

confidence: 99%

“…9(a). The conventional models in [3] and [4] are represented as parallel-connected circuits, as illustrated in Fig. 9(b) and (c), respectively.…”

Section: B Interference Of Current Paths Between Decoupling Capacitorsmentioning

confidence: 99%

“…8. The conventional model in [3] does not consider the distance between view port and the decoupling capacitors. As shown in Fig.…”

Section: B Interference Of Current Paths Between Decoupling Capacitorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

An efficient path-based equivalent circuit model for design, synthesis, and optimization of power distribution networks in multilayer printed circuit boards

Kim

Yoon

Lee

et al. 2004

IEEE Trans. Adv. Packag.

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show abstract

Bypassing, Decoupling, and Power Distribution

Barnes¹

2004

Robust Electronic Design Reference Book

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Effective Radii of On-Chip Decoupling Capacitors

P.-Vaisband¹,

Jakushokas²,

Popovich³

et al. 2016

On-Chip Power Delivery and Management

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Abstract-Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on a die or placed inside the rows in standard cell circuit blocks. The efficacy of on-chip decoupling capacitors depends upon the impedance of the power/ground lines connecting the capacitors to the current loads and power supplies. A design methodology for placing on-chip decoupling capacitors is presented in this paper. A maximum effective radius is shown to exist for each on-chip decoupling capacitor. Beyond this effective distance, a decoupling capacitor is ineffective. Depending upon the parasitic impedance of the power distribution system, the maximum voltage drop seen at the current load is caused either by the first droop (determined by the rise time) or by the second droop (determined by the transition time). Two criteria to estimate the minimum required on-chip decoupling capacitance are developed based on the critical parasitic impedance. In order to provide the required charge drawn by the load, the decoupling capacitor has to be charged before the next switching cycle. For an on-chip decoupling capacitor to be effective, both effective radii criteria should be simultaneously satisfied.Index Terms-Decoupling capacitors, power distribution systems, power supply noise, signal integrity.

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Decoupling capacitor calculations for CMOS circuits

Cited by 70 publications

References 6 publications

An efficient path-based equivalent circuit model for design, synthesis, and optimization of power distribution networks in multilayer printed circuit boards

An efficient path-based equivalent circuit model for design, synthesis, and optimization of power distribution networks in multilayer printed circuit boards

Bypassing, Decoupling, and Power Distribution

Effective Radii of On-Chip Decoupling Capacitors

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