Defect-oriented testing of Josephson logic circuits and systems

Kerkhoff, Hans G.; Speek, H.

doi:10.1016/s0921-4534(00)01611-7

Cited by 12 publications

(10 citation statements)

References 7 publications

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“…Shorts in a JJ are an example of the second kind. Our early study on this subject was published in reference [13]. The induced faults in the developed test structures will be used to validate the results of our earlier studies.…”

Section: Discussionmentioning

confidence: 80%

The detection of defects in a niobium tri-layer process

Joseph

Heuvelmans

Gerritsma

et al. 2003

IEEE Trans. Appl. Supercond.

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Abstract-Niobium (Nb) LTS processes are emerging as the technology for future ultra high-speed systems especially in the digital domain. As the number of Josephson Junctions (JJ) per chip has recently increased to around 90,000, the quality of the process has to be assured so as to realize these complex circuits. Until now, very little or no information is available in the literature on how to achieve this. In this paper we present an approach and results of a study conducted on an RSFQ process. Measurements and SEM inspection were carried out on sample chips and a list of possible defects has been identified and described in detail. We have also developed test-structures for detection of the top-ranking defects, which will be used for yield analysis and the determination of the probability distribution of faults in the process. A test chip has been designed, based on the results of this study, and certain types of defects were introduced in the design to study the behavior of faulty junctions and interconnections.

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Section: Discussionmentioning

confidence: 80%

The detection of defects in a niobium tri-layer process

Joseph

Heuvelmans

Gerritsma

et al. 2003

IEEE Trans. Appl. Supercond.

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“…There are a number of programs and tools for efficient fault injection [2,7,10,22,24,26,28,31,35,43,45,49,55,56]. There are efforts to model fault propagation and effect [5,7,12,17,19,22,23,27,28,30,32,36,38,39,40,41,44,45,47,50,52]. Coverage is a popular topic, and the meaning of coverage can vary from simple detection to complete system recovery and reconfiguration [1,2,3,4,5,10,11,12,15,16,17,18,20,21,27,29,…”

Section: Literature Surveymentioning

confidence: 99%

Designing fault-injection experiments for the reliability of embedded systems

White

2012

2012 IEEE/AIAA 31st Digital Avionics Systems Conference (DASC)

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This paper considers the long-standing problem of conducting fault-injections experiments to establish the ultra-reliability of embedded systems. There have been extensive efforts in fault injection, and this paper offers a partial summary of the efforts, but these previous efforts have focused on realism and efficiency. Fault injections have been used to examine diagnostics and to test algorithms, but the literature does not contain any framework that says how to conduct fault-injection experiments to establish ultra-reliability. A solution to this problem integrates field-data, arguments-from-design, and fault-injection into a seamless whole. The solution in this paper is to derive a model reduction theorem for a class of semi-Markov models suitable for describing ultra-reliable embedded systems. The derivation shows that a tight upper bound on the probability of system failure can be obtained using only the means of system-recovery times, thus reducing the experimental effort to estimating a reasonable number of easily-observed parameters. The paper includes an example of a system subject to both permanent and transient faults. There is a discussion of integrating fault-injection with fielddata and arguments-from-design.

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